Tutorial_PlanAhead - david-macmahon/wiki_convert_test GitHub Wiki
work in progress!! I started making this at noon on thursday hahahaha
This tutorial will teach you how to do basic timing improvement in PlanAhead. It's a work in progress, but hopefully, we'll cover some basic tasks.
All pictures can be found in the tut8 directory. No time to upload to casper.berkeley.edu
copy your tutorial project from /data/tutorials_devel/tut8 (or thereabouts) to your own directory.
I have created a simple project which has three issues. Let's build the file (already done) and try to fix them.
Important note!! follow the instructions in this order. Some hackery was done to make the designs break the way I want them to.....
You can open the design 'tut8.slx', if you want. DON'T BUILD IT!! The design has already been built. We are targetting an FPGA clock rate of 350 MHz, which we can't achieve with this design. We will open it in planAhead and figure out what's wrong
1. Open your design in planAhead.
First, you have to initialize the Xilinx environment. On the tutorial computers this is done by running
source /opt/xilinx/14.7/ISE_DS/settings64.sh
then, you can type 'planAhead' and get off to the ball-game.
Now, to open your design in planAhead.
2. build a project with your ISE place and route results
<tut8_newP.png>
Click "new project", put it in your directory and choose "import ISE place and route results", the option we will always use when analyzing timing results from a finished design.
<tut8_projName.png> <tut8_import.png>
Add your project files. You need to add both the
<tut8_add.png>
implementation directory (<model_name>/XPS_ROACH_BASE/implementation), and top level file (<model_name>/XPS_ROACH_BASE/implementation/system.ngc) <tut8_stuff_added.png>
Next page, add your ucf file. this file describes pin locations, timing constraints and placement constraints. Everything about where modules go on the FPGA, and how the FPGA design interacts with the outside world, is described in this file. find it at (<model_name>/XPS_ROACH_BASE/implementation/system.ucf) <tut8_ucf.png>
next page, planahead has already identified your device. click through
finally, you need to give planahead your placement and timing file. Placement file describes where the MAP tool placed all the components in your design, whereas the timing file describes how slow your paths were. find both files in the same directory (<model_name>/XPS_ROACH_BASE/implementation/system_map.ncd) (<model_name>/XPS_ROACH_BASE/implementation/system_map.twx) <tut8_ncd_twx.png>
Click through and open your design. If it asks, choose "open implemented design".
you should see something like this:
<tut8_long_path.png>
Lets look at our timing reports. First, consider the worst failing path (a whopping 8ns). Let's double click on this one. you should see something like this:
<tut8_long_path_summary.png>
There's a lot going on in this tab. You can see where this path starts at, stops at, and how fast we needed the clock to run ("requirement"). We see our how long the path took, and therefore how far we were off by ("data-path delay" and "slack")
Below that, you see a breakdown of the data-path. This shows what components were involved in the delay, and how long each one took. "net"s are where signals flow between components. we need the signal to make it through within the ammount of time we have allocated for our target clock rate.
It's important to note that in this case, planAhead is oddly rounding all numbers to the nearest nanosecond. I can't quite pin down why this is, but it should not be the case! I have never seen this happen before. *shrug*.
In any case, look at the breakdown of the delay. in this case, planahead is saying that this path took 8ns (out of 2ns), 100% of which is route. If this number is anything above 60% and your design isn't clocking fast enough, be strongly suspicious of a bad placement. Inspecting the device view, we see that this signal is going across the chip. I placed two pblocks far from each other, forcing this bad performance.
We can get an idea for how big of a deal this is, by clicking on the list of timing results (we double clicked on one earlier) and hitting ctrl-A for "select all". you can click on the device tab above and view where all these paths are going on the chip. There's a big group of them going from the northwest side of the chip to the southeast. Click on the offending pblock in the southeast and drag it over to the northwest. <tut8_moved_pblock>
Save the design, choosing to use the same constraints name. Now open that constraints file as shown below
<tut8_open_ucf.png> (look at the highlighted file)
Now this file is a copy that PlanAhead made for us; let's save it back over the original so that CASPER_XPS can use it: click "file->save as", and save to (<model_name>/XPS_ROACH_BASE/data/system.ucf).
Go back to matlab and uncheck everything except EDK/ISE/bitgen. Run again. it will not pass timing. Let's save some time by just importing placement and timing files instead of making a new project. click file -> import -> import placement. do the same for file -> import -> import timing. Now, you should see new errors!
Open the top one now. Notice that this one is different (and less bad) <tut8_many_adders> this error has many adders involved. If everything was working well, you would see a little bit of delay on each component. This time, we're having problems. In any case, if you look at the component names, this is because I chained several big adders together without any delay between them. Notice how the instance path names relate directly to components in the module. Add a cycle or two of latency to each of them, and recompile. Make a new project, as before, and consider the results. much better!
I don't think I have enough time to continue writing the tutorial after this, so this is where the buck stops! We can improvise during the tutorial :-)