Toolflow_Introduction - david-macmahon/wiki_convert_test GitHub Wiki

The following is copied directly from an email from Henry Chen to the CASPER mailing list on 26 Nov 2008. Updated: to include changes

Toolflow Basics

A Simulink/SysGen design is created as usual. The only difference is that the use of Gateway Blocks is restricted, and any I/O for the design must go through a block from the provided CASPER_XPS System Blockset. The reason for this is that the "yellow blocks" are tagged with a parameter that uniquely identifies it as a supported toolflow block. It should be noted that this is all a yellow block does. For the most part, it contains no implementation code whatsoever. It is simply a collection of gateway blocks and a tag.

When you run casper_xps, the first thing the scripts do is to go through every single block in the design and look for any and all of these tags. Whenever a tagged block is found, a Matlab object is created (all of the @xps_--- directories in the xps_library are actually Matlab object constructors; see Matlab documentation for more info on Matlab objects). These objects are used to store parameters and functions needed to help configure the interface.

After the objects are created, System Generator is run as if you had opened up the SysGen token and clicked on the "Generate" button. The settings on the SysGen token are set by the MSSGE block from the CASPER_XPS System Blockset so that the toolflow knows where to find the results, and how to interpret them. In this case, a netlist is generated.

Then, a base system is extracted from xps_base. The base system is a skeleton EDK project that is customized to the particular board you want to compile for. It has all of the clocking and processor infrastructure you need to run your design. In addition, currently each base system comes with all of the supported interface pcores for that board. Once the base system is extracted, the netlist from System Generator is used to create an EDK pcore.

The structure of EDK projects and pcores are documented by Xilinx in their "Platform Specification Format Reference Manuals" for each major EDK release.

At this point, the Matlab objects come back into play. Each of them have a number of member functions to customize the EDK project according to their stored parameters. For example, an adc object has fields for what pcore the EDK project needs to instantiate. It also knows that the pcore it will instantiate has certain ports that need to be connected to FPGA IO resources and certain ports that need to be connected to the ports of the System Generator design. This is why the use of Gateway blocks are restricted to yellow blocks, because Gateway blocks translate to ports on the design netlist, and the yellow block wrapper provides information about how to connect these ports to the corresponding interface pcore.

Using these member fields and member functions, each object writes to the project's MHS, MSS, and UCF files to instantiate one or more pcores corresponding to each yellow block's interface. Your System Generator design's pcore is also instantiated and connected to the various interfaces you've put in.

Since the current generation of boards uses Virtex-II Pro FPGAs with embedded PowerPC 405s, drivers to interact with some of the yellow blocks are also included in the project. These software drivers are packaged with the base system, and the XMP project file is modified to include them when used.

The software that runs on the PPC is a modified TinySHell that gives you a shell-like environment for accessing memory regions mapped to the PPC bus. To add custom functions available to the user from the shell, the TinySH code itself needs to be modified. When you want custom software, there are certain tags you need to insert into your code so that the toolflow knows how to insert them into TinySH, such as if you want it to run in the main loop, or if you want it to be a user-callable function.

Once all the project files are written, the script calls XPS in batch mode to compile the EDK project, at the end of which pops out your bitstream and/or BORPH executable.

References