Timing_Errors - david-macmahon/wiki_convert_test GitHub Wiki

Append random tidbits about timing problems that might be helpful to others.

MAP Fails

Under some circumstances, the compiler can tell that a design will not meet the necessary timing constraints before it even tries to run PAR, and the compilation will fail during the map phase. But the compiler doesn't generate timing reports until the PAR phase, so it will not generate a timing report in these cases. Needless to say, this makes it difficult to track down the cause of your timing error.

The error message will look something like this:

ERROR:Pack:1653 - At least one timing constraint is impossible to meet because
   component delays alone exceed the constraint. A timing constraint summary
   below shows the failing constraints (preceded with an Asterisk (*)). Please
   use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and
   PCF files to identify which constraints and paths are failing because of the
   component delays alone. If the failing path(s) is mapped to Xilinx components
   as expected, consider relaxing the constraint. If it is not mapped to
   components as expected, re-evaluate your HDL and how synthesis is optimizing
   the path. To allow the tools to bypass this error, set the environment
   variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1.


   For more information about the Timing Analyzer, consult the Xilinx Timing
   Analyzer Reference manual; for more information on TRCE, consult the Xilinx
   Development System Reference Guide "TRACE" chapter.

Mapping completed.
See MAP report file "system_map.mrp" for details.
Problem encountered during the packing phase.

When this happens, you need to tell the compiler to ignore the fact that it won't meet timing, map it anyway, and then try to run PAR. It will still fail, but now you will have a timing report to tell you why. As the error message says, you need to set the environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1 and recompile.

PAR Fails

To be documented, lol.