TVG's,_Software_Registers,_and_Snapshots - david-macmahon/wiki_convert_test GitHub Wiki
DDC
DDC TVGs
tvg: Puts test data directly into the xaui link to the BEE2
| Mux register (0 for passthrough 1 for tvg data) | ddc_en |
| Enable counter on test data (0 to count through brams, 1 to stop counting) | counter_n_en |
| Real test data | tvg/ram_re |
| Imaginary test data | tvg/ram_im |
DDC Scopes
snap_adc: Records 8 bit real samples (concatenated to get 32 bits) directly from the ADC.
| Write enable register | snap_adc_we |
| Control register | snap_adc/ctrl |
| Output bram | snap_adc/bram |
snap_mixer: Records 8 bit real samples (concatenated to get 32 bits) directly from the mixer. (Note: there is no scope on the imaginary output of the mixer)
| Write enable register | snap_adc_we |
| Control register | snap_adc/ctrl |
| Output bram | snap_adc/bram |
snap_out: Records 16 bit (0 padded to make 32 bits) real and imaginary samples directly from the dec_fir.
| Write enable register | snap_we |
| Control register | snap_out/ctrl |
| Real output bram | snap_out/bram_msb |
| Imaginary Output bram | snap_out/bram_lsb |
snap_fft: Records 32 bit power spectrum from a 2^12 point fft on the decimated and downshifted signal.
| Write enable register | snap_fft_we |
| Control register | snap_fft/ctrl |
| Real output bram | snap_fft/bram |
Registers:
"data_sel" - Data output MUX selector (0 = from PFB; 1 = from TVG)
"snap/addr"
"snap/bram" - SNAP block on output of data_out MUX
"snap/ctrl"
"snap_WE" - Write enable pin for SNAP block
"tvg/bram_wr_reg" = Register used to fill BRAMs in TVG.
"tvg/im_we" - Write enable pin for "snap_im" block
"tvg/ram_im" - BRAM for imaginary source
"tvg/ram_re" - BRAM for real source
"tvg/re_we" - Write enable pin for "snap_re" block
"tvg/snap_im/addr"
"tvg/snap_im/bram" - Snap block connected to imaginary block ram
"tvg/snap_im/ctrl"
"tvg/snap_re/addr"
"tvg/snap_re/bram" - Snap block connected to real block ram
"tvg/snap_re/ctrl"
"tx_nvalid" - See below
"sync_period/sync_select" - MUX select pin for sync period; default is 2^28-1
"sync_period/sync_period" - Manually set sync period; MUX must be 3
"ddc_en" - Set HI to pull data from DDC blocks
"rb_sma_in" - Input SMA for radar blanker
"blank_radar" - Software register to enable "rb_sma_in"
"beam_switcher/switchyard_BRAM" - BRAM LUT for switching beam/pol
"beam_switcher/max_addr" - When "switchyard_BRAM" reaches "max_addr", it returns to beginning
"beam_switcher/beam_number" - Output software register that contains beam encoder value
LEDs
0 = sync pulse
4 - 7 = 4 bits of the 8 bit beam/pol switcher encoding
PFB
TVGs
data_mux_in: Bypass data from the DDC
| Mux register (0 for passthrough 1 for tvg data) | data_mux_in/data_sel |
| data_mux_in/tvg/tvg_ctrl | |
| Real test data | data_mux_in/tvg/ram_re |
| Imaginary test data | data_mux_in/tvg/ram_im |
sync_in_mux: Bypass sync from the DDC
| Mux register (0 for passthrough 1 for generated sync) | sync_in_mux/sync_sel |
| Generated sync period | sync_in_mux/sync_per |
data_out_mux: Put test data directly into the output link to the CT, bypassing the output of the PFB
| Mux register (0 for passthrough 1 for tvg data) | data_out_mux/data_out_sel |
| data_out_mux/tvg/tvg_ctrl | |
| Real test data | data_out_mux/tvg/ram_re |
| Imaginary test data | data_out_mux/tvg/ram_im |
sync_out_mux: Put a generated directly into the output link to the CT, bypassing the sync from the PFB
| Mux register (0 for passthrough 1 for generated sync) | sync_out_mux/sync_sel |
| Generated sync period | sync_out_mux/sync_per |
Scopes
snap_xaui: Records complex data from the DDC.
| Write enable register | snap_xaui_we |
| Control register | snap_xaui/ctrl |
| Real output bram | snap_xaui/bram_msb |
| Imaginary output bram | snap_xaui/bram_lsb |
snap_pfb: Records complex data from the PFB FIR.
| Write enable register | snap_pfb_we |
| Control register | snap_pfb/ctrl |
| Real output bram | snap_pfb/bram_msb |
| Imaginary output bram | snap_pfb/bram_lsb |
snap_fft: Records complex data from the PFB FFT.
| Write enable register | snap_fft_we |
| Control register | snap_fft/ctrl |
| Real output bram | snap_fft/bram_msb |
| Imaginary output bram | snap_fft/bram_lsb |
Registers:
"data_mux_in/data_sel" - Selects input to PFB block. 0 = from gpio links; 1 = TVG
"data_mux_in/tvg/*" - Input mux TVG
"data_out_mux/data_out_sel" - Selects output to be sent to next block. 0 = from FFT; 1 = TVG
"data_out_mux/tvg/*" = Output mux TVG
"fft_shift" - Sets FFT shifting schedule. See FFT documentation.
"rx_empty" - XAUI status register. HI when RX buffer empty.
"rx_linkdown" - XAUI status register. HI when link not established.
"rx_valid" - XAUI status register. HI when valid data available.
"snap_fft_we" - WE register for "snap_fft" block.
"snap_fft/*" - 4k long SNAP64 block on output on FFT block
"snap_pfb_we" - WE register for "snap_pfb" block.
"snap_pfb/*" - SNAP64 block on output of PFB_FIR block
"snap_xaui_we" - WE register for snap_xaui block
"snap_xaui/*" - Snap block on output of XAUI
"sync_in(out)_mux/sync_out_sel" - Input sync mux select. 0 = from gpio links; 1 = TVG
"sync_in(out)_mux/sync_period" - Number of clocks between two sync pulses if generating sync pulse
"xaui_reset" - toggles "rx_valid" pin on input XAUI block
Additional registers in XAUI designs:
"snap_pfb_delay" - Delays the triggering of the "snap_pfb" block
"snap_fft_delay" - Delays the triggering of the "snap_fft" block
"gpio0_xaui1" - Toggles output method: 0 = gpio; 1 = XAUI
"tx_n_valid" - Toggles tx_valid LO by setting this register HI.
'''LEDs:
0 = sync
CT
TVGs
tvg_in: Bypass data from the PFB
| Mux register (0 for passthrough 1 for tvg data) | data_in_sel |
| tvg_in/tvg_ctrl | |
| tvg_in/bram_wr_reg | |
| Real test data | tvg_in/ram_re |
| Imaginary test data | tvg_in/ram_im |
sync_in: Bypass sync from the PFB
| Mux register (0 for passthrough 1 for generated sync) | sync_in_sel |
| Generated sync period | sync_period |
tvg_out: Put test data directly into the output link to the FFT, bypassing the output of the corner turn
| Mux register (0 for passthrough 1 for tvg data) | data_out_sel |
| tvg_out/tvg_ctrl | |
| tvg_out/bram_wr_reg | |
| Real test data | tvg_out/ram_re |
| Imaginary test data | tvg_out/ram_im |
sync_out: Put a generated directly into the output link to the FFT, bypassing the sync from the corner turn
| Mux register (0 for passthrough 1 for generated sync) | sync_out_sel |
| Sync period | sync_out_period |
Scopes
snap_in: Records complex data from the PFB.
| Write enable register | snap_in_we |
| Control register | snap_in/ctrl |
| Real output bram | snap_in/bram_msb |
| Imaginary output bram | snap_in/bram_lsb |
snap_out: Records complex data being sent to the FFT (if test data is being sent then it will be captured by this tvg).
| Write enable register | snap_out_we |
| Control register | snap_out/ctrl |
| Real output bram | snap_out/bram_msb |
| Imaginary output bram | snap_out/bram_lsb |
Registers:
"sys/data_in_sel" - Selector for input data MUX (0 = from previous FPGA, 1 = TVG)
"sys/data_out_sel" - Selector for output data MUX (0 = from model blocks, 1 = TVG)
"sys/snap_in/*" - SNAP64 block on input of CT block
"sys/snap_in_we" - WE register for "snap_in" SNAP block
"sys/snap_out/*" - SNAP64 on output of CT block.
"sys/snap_out_we" - Manual WE register for "snap_out" block
"sys/sync_period" - Sets input sync period of self-generated sync pulse
"sys/sync_in_sel" - Selector for input sync MUX (0 = from previous FPGA, 1 = TVG)
"sys/sync_out_period" - Sets output sync period of self-generated sync pulse
"sys/sync_out_sel" - Selector for input sync MUX (0 = from previous FPGA, 1 = TVG)
"sys/tvg_in(out)/bram_wr_reg"
"sys/tvg_in(out)/ram_im" - Input (output) TVG's
"sys/tvg_in(out)/ram_re" -
"sys/tvg_in(out)/tvg_ctrl"
"sys/led" - Error register
"sys/reset_led" - Resets error register "led"
For models with XAUI links:
"snap_in_delay" - Delays triggering of "snap_in" block for N clocks after sync goes HI.
"gpio0_xaui1_in" - Selects input method: gpio = 0; XAUI = 1
"snap_out_delay" - Delays triggering of "snap_out" block for N clocks after sync goes HI.
"gpio0_xaui1_out" - Selects output method: gpio = 0; XAUI = 1
"tx_nvalid1" - Toggles "tx_valid" LO for the XAUI output port 1
"tx_nvalid2" - Toggles "tx_valid" LO for the XAUI output port 2
LEDs:
0 = sync pulse
1 = cmdAck1
2 = cmdAck2
4 = any_error
FFT
TVGs
None
Scopes
snap_fft: Records complex data from the CT.
| Write enable register | snap_fft_we |
| Control register | snap_fft/ctrl |
| Real output bram | snap_fft/bram_msb |
| Imaginary output bram | snap_fft/bram_lsb |
Registers:
"snap_fft_we" - WE for SNAP block on input to FFT model
"snap_fft/bram_lsb(msb)" - SNAP block on input to FFT model
"snap_fft/ctrl"
"snap_fft/addr"
"fft_shift" - Sets FFT shift schedule
Models with XAUI links:
"gpio0_xaui1_in" - Selects input format: 0 = gpio; 1 = XAUI
"gpio0_xaui1_out" - Selects output format: 0 = gpio; 1 = XAUI
"snap_delay" - Delays trigger of "snap_fft" block by some given number of clocks after the sync pulse
"tx_n_valid" - Toggles the XAUI "tx_valid" pin LO
LEDs:
0 = sync pulse
Thresholder
TVGs
ct_in_mux: Bypass data from the corner turner
| Mux register (0 for passthrough 1 for tvg data) | ct_in_mux/data_sel |
| ct_in_mux/tvg/tvg_ctrl | |
| ct_in_mux/tvg/bram_wr_reg | |
| Real test data | ct_in_mux/tvg/ram_re |
| Imaginary test data | ct_in_mux/tvg/ram_im |
sync_ct_mux: Bypass sync from the corner turner
| Mux register (0 for passthrough 1 for generated sync) | sync_ct_mux/sync_sel |
| Generated sync period | sync_ct_mux/sync_per |
fft_in_mux: Bypass data from the fft
| Mux register (0 for passthrough 1 for tvg data) | fft_in_mux/data_sel |
| fft_in_mux/tvg/tvg_ctrl | |
| fft_in_mux/tvg/bram_wr_reg | |
| Real test data | fft_in_mux/tvg/ram_re |
| Imaginary test data | fft_in_mux/tvg/ram_im |
sync_fft_mux: Bypass sync from the fft
| Mux register (0 for passthrough 1 for generated sync) | sync_fft_mux/sync_sel |
| Generated sync period | sync_fft_mux/sync_per |
Scopes
ct_in_mux/snap64_ct: Records complex samples coming over the gpio from the corner turner
| Write enable register | ct_in_mux/snap_ct_we |
| Control register | ct_in_mux/snap64_ct/ctrl |
| Real output bram | ct_in_mux/snap64_ct/bram_msb |
| Imaginary output bram | ct_in_mux/snap64_ct/bram_lsb |
fft_in_mux/snap64_fft: Records complex samples coming over the gpio from the fft
| Write enable register | fft_in_mux/snap64_fft_we |
| Control register | fft_in_mux/snap64_fft/ctrl |
| Real output bram | fft_in_mux/snap64_fft/bram_msb |
| Imaginary output bram | fft_in_mux/snap64_fft/bram_lsb |
Registers: (abbreviated)
"ct_in_mux/*" - Input data MUX for CT data
"ct_in_mux/snap64_ct/*" - SNAP64 block on CT input
"fft_in_mux/*" - Input data MUX for FFT data
"fft_in_mux/snap64_fft/*" - SNAP64 block on FFT input
"rec/rec_fifo2"- Unused
"rec/snap_bins/*" - Snap blocks connected to the outputs just before entering the 10GeB block
"rec/snap_pwr/*" - BINS = FFT and PFB bins and EVENT boolean
"rec/snap_thr/*" - THR = Threshold value (mean power * scale); PWR = Power
"sync_ct(fft)_mux" - Input mux for CT (FFT) sync pulse
"thr/comp1(2)/thr_lim" - Limits number of events per coarse PFB bin for each polarization
"thr/scale/p1(2)_scale" - Value to scale the average power by
"thr/snap_*/" - Snap blocks
"thr/comp1/in_*/bram" - Snap blocks (see model)
"thr/comp1/out_*/bram" - Snap blocks
"snap_en" - Enable pin for many of the snap blocks throughout design
For blocks with XAUI links:
"gpio0_xaui1" - Selects input method: gpio = 0; XAUI = 1
"sync_ct_mux/snap_delay" - Delays triggering of "snap64_ct" block by N clocks after sync
"sync_fft_mux/snap_delay" - Delays triggering of "snap64_fft" block by N clocks after sync
LEDs:
0 = sync pulse from CT block
1 = sync pulse from FFT block
2 = p1_event
3 = p2_event
4 = p1_we
5 = p2_we