RoachPDRNotes - david-macmahon/wiki_convert_test GitHub Wiki

Design Review at BWRC - 29 June 2007

Notes:

0. Dan to investigate availability/suitability of ML561 and ML505 boards.

1. Jumper selectable GPIO Vio.

2. QSH - leave room for daughterboard.

3. ATX PSU connector should be right angle.

4. Confirm if GCLK inputs have output drivers.

5. 440 EPx JTAG 8x2 (pin missing BDI2000 - see Pierre).

6. Xilinx JTAG to PPC GPIO.

7. DDR2 Termination as per Pierre's sketch.

8. Don't connect SD card to SPI from the PPC.

9. Use SD card.

10. Data lines and selectmap inverted A0 -> A31 D0 -> D15.

11. Wide address space desirable for Borph access to DRAM.

12. QDRII+ = 3.5 banks each - share 1 bank.

13. Leave out NAND Flash.

14. Fan speed and temperature monitor.

15. Write Spec.

16. 1V core voltage generated from lower voltage (5V or 3.3V).

17. Do unbuffered DDR2 first (controller is easier).

18. Add clock capable LVDS on Samtec QSH. Need to confirm pins for BEE3 compatibility.

19. More LED's, more GPIO, DIP Switch, Reset buttons.

20. What license is required for Actel programming, and what is the cost of the programmer and software? - Software is free download (registration required) from http://www.actel.com/download/reg/default.aspx?f=FlashPro60. Programmer is the FlashPro3, available from Mouser at $130 or from local Actel rep.

21. Connect SPI.

22. SD card access - must open box.

23. USB on back panel.

24. 32 GB allowed for in DDR2 specification.

25. Roach mail list to be created.