Review_Notes - david-macmahon/wiki_convert_test GitHub Wiki

Review Notes

No	Description	Sheet/Refdes	Resolution	Impact	Status
1	Draw Schematics	All	Francois to draw	None	Ready for review
2	QDRII+ JTAG connected to test points	Sh 1,14,15	TBD	No dedicated connector	OK
3	No 5VAUX on Auxiliary power connector	Sh 2	REMOVE	Need additional connector/use larger terminal block?	REMOVED
4	Combine J29, J30, J45 and SW5 on single header	Sh2	OK	Slightly easier placement	DONE
5	Pushbutton switches should be button on top, or header to front panel, not right angle	Sh 2, 23	OK	Usability	DONE
6	Mode signals must be connected to CPLD	Sh 1, 16, 24	OK	Add connections	DONE
7	Peripheral bus control signals to V5 (PERCLK missing)	Sh 1, 21, 25	OK	Swap for Address line. Only clock required, bus mastering not needed, rather use DMA	DONE
8	PowerPC Power Supply pins must be separated from V5 power	Sh 17, 18	Remove regulators in stead	Shared supply rails	DONE
9	Implement DMA for Peripheral bus to V5 interface	Sh 1, 13, 25	Add	Swap for Address lines - Signals multiplexed with higher order address lines	DONE
10	Add Interrupt from V5 to PPC	Sh 1, 13, 23, 25	Add	GPIO's shared	DONE
11	Partial reconfiguration via JTAG only	N/A	OK	None	Note
12	10-20ps line matching will require compensation for package delays	N/A	OK	Package models required	Note
13	DIMM's may be susceptible to vibration	N/A	OK	None	Note
14	Should have 512MB of RAM for PPC	N/A	OK	None	Note
15	Check 4 pin fan availability	J19, J20, J21	3 pin fits on 4 pin connector	No speed control on 3 pin fans	DONE, re-confirmed
16	KAT team have time available for investigation of thermal design/v5 cooling	U15	OK	None	Note
17	Remove screw terminal power	Sh 3: J17, FH1, FH2, FH3	OK	ATX Power only	DONE
18	Replace some V5 decoupling (220nF) with 10uF ceramics	Sh 4	OK	Broader range decoupling	DONE
19	All config pins must be connected to the appropriate PPC pins	Sh 1, 16, 23, 25	OK	Improve bus access	DONE
20	Add series termination to clock nets, inc PERCLK	Sh 25	OK	Better signal integrity	DONE
21	Add protection diodes to the differential clock inputs	Sh 7	OK	Foolproof	DONE
22	Must have at least one DC coupled SMA input for PPS	Sh 7	OK	Change	DONE
23	Investigate alternatives for large termination on clocks	Sh 7	TBD	Series termination recommended	DONE
24	Some experience of problems with LVDS oscillators	Sh 7	Dan to advise	Component selection (dual source)	DONE
25	Add every other pin ground to GPIO headers, ensure shrouded/female headers	Sh 13	OK	Change	DONE
26	PPC peripheral address bus could be reduced to ~24 bits to free up IO's. Must be able to address all block RAM (8784Kb) and QDR's (currently 36Mb X 2)	Sh 25	OK	None	Note
27	1 gigabit bandwidth target for PPC/V5 interface. Good match with 16/66MHz.	Sh 25	OK	None	Note
28	512Mbit NOR Flash OK	Sh 25	OK	None	Note
29	RS232 connector in rear IO space is not essential	Sh 25	OK	None	Note
30	PPC powered of same voltages as V5, share PSU	Sh 17, 18	OK	Remove regulators, link nets	DONE
31	Check Linux support for NSC Ethernet Phy	Sh 20	Supported by U-boot	OK	DONE
32	Check PPC DDR termination in HyperLynx	Sh 22	Check	Possible series termination	TBD
33	Add reset from Actel to PPC	Sh 1, 2, 24	OK	Change	DONE
34	Use SD compatible connector	Sh 24, J23	OK	Change	DONE
35	Write up power sequencing	N/A	OK	Document	TBD
36	Write up configuration	N/A	OK	Document	TBD
37	VRN/VRP pins not required for LVDS	Sh 5, 6, 12	OK	Remove reference resistors, 10 pins available	DONE
38	ECL series termination to be used on clock input	Sh 7	OK	Change, eases placement	DONE
39	PPC temperature diode connected to monitor	Sh 1, 2, 23	OK	Can monitor	DONE
40	Pull DIR control pins to correct state to prevent clash	Sh 13	OK	Add pull-up/down	DONE
41	Change Serial EEPROM's to SOIC	Sh 25, U38-40	OK	Change PKG_TYPE	DONE
42	Add decoupling cap to comparator VN input	Sh 7	OK	Add caps	DONE
43	Change PB switches to smaller version	Sh 23, SW1	OK	Change component	DONE
44	Is voltage selection required on comparators?	Sh 7, U4, U5	No	Thresholds can still be set by resistor change	DONE
45	Do not require R and C on comparator input	Sh 7, C5 and R101, C15 and R102	OK	Nice to have, keep	DONE
46	Adjust termination/biasing resistors on comparator inputs for stable output	Sh 7, R136, R137, R116, R104, R102, R107, R103, R115, R108	Discuss	Programmable hysteresis is enough	DONE
47	ZQ's should be terminated to VSS	Sh 14, 15	OK	Correct	DONE
48	Add pull-downs to DOFF_...	Sh 14, 15	OK	Add pull-down	DONE
49	Vref to VREF_QDR..	Sh 14, 15	OK	Correct	DONE
50	QDRII+ JTAG TCK must be pulled down	Sh 14, 15	OK	Correct	DONE
51	VDD_QDR2_ net is not connected	Sh 14, 15	OK	Change to 1.8V	DONE
52	CAL_DONE and COMPARE_ERROR signals are test only and could be re-used	Sh 14, 15	None	Spare pins	TBD
53	Check ADI comparator availability	Sh 7, U4, U5	Check	Full production	OK, MOQ 50
54	Check for second sources for oscillators	Sh 7, X2-3, Sh 8, X1, Sh 9, X4	Check	Epson Toyocom, Vectron, Silabs	OK
55	Logic levels on DIR pins wrong	Sh 13, U10-11,13-14	OK	Correct, add translators	DONE
56	Add and connect G38-G74 to CX4 connector	Sh 8, 9 P3	OK	Add pins	DONE - check G19/G56
57	Add boot configuration control pins from Actel to CPLD	Sh 1, 2, 24	OK	Add pins	DONE
58	Remove U3	Sh 17, U3, C21-31	OK	Correction	DONE
59	Correct R220,221	Sh 10	OK	Correction	DONE

Schematic Review Issues and Notes