MyHDL_toolflow - david-macmahon/wiki_convert_test GitHub Wiki
Desired Features
The next generation tool flow should have the following features from the MSSGE toolflow:
Well-optimized, parameterized primitives
- All of the DSP libraries are made up of a handful of blocks from the
XSG blockset which typically invoke coregen to provide efficient
implementations.
- We could also use coregen, but we need a bit and cycle accurate
simulation model, ideally accessible from Python (rather than
HDL).
- Can we use the MyHDL cosimulation capability to simulate a Verilog model of the core provided by coregen? Would this be too slow?
- Otherwise, are the basic blocks simple enough that we can confidently make our own MyHDL simulation models that are still implemented as coregen cores?
- We could just write behavioral MyHDL descriptions for each of
the core blocks, which would become HDL.
- This seems like potentially a lot of tedious, error prone work.
- Are synthesis tools good enough to provide implementations as good as coregen cores?
- Coregen provides the ability to specify pipelining/latency. Is there an easy way to do this in MyHDL?
- We could use the HDL macros provided by Xilinx for many primitives, described e.g. Virtex-5 Libraries guide for HDL designs
- We could also use coregen, but we need a bit and cycle accurate
simulation model, ideally accessible from Python (rather than
HDL).
Single, synchronous clock domain
- While it limits some flexibility, the current single clock domain
(for the simulink design) paradigm works well for CASPER
applications, and limits confusion for new users.
- Ideally we'd like this to be transparent in the MyHDL based
toolflow.
- Could do this with base classes, global variables, or decorators
- Ideally we'd like this to be transparent in the MyHDL based
toolflow.
Yellow block interfaces
- We will need a library of objects that represent the available
peripherals to take the place of the yellow blocks.
- It should be fairly straightforward to translate the current yellow block scripts to Python to generate the necessary interfaces and .mhs etc files.
Fixed point arithmetic with automatic bit-growth
- Currently, MyHDL seems to only support integer arithmetic. It should be straightforward to extend the integer bit-vector (intbv) type included in MyHDL to a fixed point type. Perhaps can leverage work from other fixed point python libraries. In fact, it looks like someone has implemented a fixed point extension for MyHDL here.
One-click generation
- The current toolflow encapsulates a large number of tedious steps
automatically into a single "Run XPS" button click. We'd like to
maintain this level of ease of use.
- The Matlab scripts that provide the functionality of the "Run XPS" button should be fairly straightforward to port to Python. Part of this work will be replicating the yellow block functionality described above.