MSSGE_Toolflow - david-macmahon/wiki_convert_test GitHub Wiki

The MSSGE toolflow (short for Matlab/Simulink/System Generator/EDK) is the platform for FPGA-based CASPER development, which stitches together several design and implementation environments.

It is better known as the bee_xps toolflow, which was developed at the Berkeley Wireless Research Center (BWRC) as a high-level design tool for the BEE and BEE2 platforms. We have extended it to work with all other CASPER boards as well. It provides a graphical Matlab/Simulink design environment using the Xilinx System Generator Toolbox, and abstracts the Xilinx implementation details behind a one-click compile interface.

For installation instructions, see the MSSGE Toolflow Setup page.

Components

Matlab

Matlab provides a scriptable back-end for Simulink. All mask scripts are written in the Matlab language.

Simulink

Simulink serves as both a schematic capture tool and a design simulation environment for system models targeted for CASPER FPGA boards.

System Generator

System Generator translates Simulink schematics into HDL code (either VHDL or Verilog) during design compilation. It also enables design simulation from within the Simulink environment.

EDK

EDK (Embedded Development Kit) compiles the generated HDL code into a bitstream that runs on the targeted FPGA.

Design Flow

  1. Create a Simulink model.
  2. Compile with BEE XPS.
  3. Program your board.
  4. Test, and repeat.