How_to_manually_build_a_design - david-macmahon/wiki_convert_test GitHub Wiki

NOTE: This page is still being written, and is probably not useful in its current state.

To get a better understanding of the internals behind bee_xps and the MSSGE toolflow, we suggest going through the steps to build a design by hand. To begin, download the model file:

{{mdl|Toolflowdemo.mdl|Toolflowdemo.mdl}}

The design uses the 7.1 libraries, but the steps are similar for a 10.1. Once you have opened the Toolflowdemo.mdl in Simluink, double-click on System Generator and make sure that

iBOB  -- xc2vp50   --> -7 (speed grade) --> 1152    (pin count) BEE2  -- xc2vp70   --> -7               --> 1704 ROACH -- xc5vsx95t --> -1               --> 1136

Create sysgen directory in demo: target directory: ./demo/sysgen (can really be anything)

Synthesis Tool: XST

FPGA clock period (ns) can be set (10ns is 100MHz,5ns is 200MHz ) but this will be overwritten by the .ucf file

1. Generate netlist (click generate) gives verilog or VHDL output with input and output ports. double click on System Generator click generate

Making a pcore out of a simulink design

2. Take XPS_iBOB_base.zip and put it in (use export to get rid of .svn files)

  • ase system has all the pcores
  • pcore - Peripheral Core (cores for yellow blocks)

3. create demo\XPS_iBOB_base\pcores\demo_v1_00_a\data (does it need v1_00_a?) 4. create demo\XPS_iBOB_base\pcores\demo_v1_00_a\netlist

5. create demo\XPS_iBOB_base\pcores\demo_v1_00_a\data\demo_v2_1_0.mpd (micro pro def ,text files)

6. create demo\XPS_iBOB_base\pcores\demo_v1_00_a\data\demo_v2_1_0.bbd (micro pro def ,text files)

7. go into demo\sysgen, demo_cw_complete.ngc is the output file we want

8. go into sysgen\synth_model, demo_cw_complete.ngc is the output file we want

cp demo_cw_complete.ngc demo\XPS_iBOB_base\pcores\demo_v1_00_a\netlist\demo.ngc

9. go back Write the mpd | making a pcore out of a simulink design, then we'll take yellow block pcores and combine them for final bitstream need to define all ports the come with yellow blocks, starting with ADC

10. (IP Creation (Pcore definition)/IP syntheis ) Go back to writing the .bbd

Files

demo.ngc

11. In XPS_iBOB_base, edit system.mhs - uncomment lines we want to use, delete lines we dont't want (this would be best done when viewing an example file

  • add in XSG IP core (instantiating Simulink IP core)
  • add in bram_if ( bram is actually 3 pcores)
  • add in bram_block
  • add in opb_bram_if_cntlr
  • add in opb_register_ppc2simulink (software register: demo/syncgen/reset)
  • add opb_register_simulink2ppc (software register: demo/sum)
  • add in adc_interface (demo/adc)
  • add in additional adc ports

note 'p' and 'n' are external ports, need to specify DIR = I , SIGIS = CLK , CLK_FREQ = 200000000

12. Then need to edit the system.mss template

This file is the software specifications which drivers ppc should use

  • add in instances of software registers

13. Then need to edit the data/system.ucf template, removing what we don't want, commenting in the things we (User constraint file)

UCF file and Netlist ===> NGD Build ==> NGD generic database

One adc controller for both

only external ports are from the yellow blocks

14. xps -nw system.xmp

XPS% run bits - doesn't include software

will create the bit file.