HDL_toolflow - david-macmahon/wiki_convert_test GitHub Wiki
HDL based toolflow
We have finally settled on a design for the new toolflow. It will be based on a library of parameterized primitives wrapped with python using the MyHDL framework. This will allow the design of higher level DSP blocks using python function calls to these primitives.
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Bus Management
- Precompiler Directives?
- Possibly manage in the MyHDL convert function?
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Clock management
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Base Design
- Clocking Infrastructure
- WB/EPB Bridge
- Permanent Registers
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Clock Domain Crossing
Primitives
The Primitives will have the option to instantiate Xilinx or Altera primitives or our parameterized ones. There will also be options to instruct the synthesizer how to implement the primitives in the fabric, be it as a DSP slice, memory etc. This will aid in optimization of the DSP blocks.
Primitive Modules
| Module | Description | Developer/s | Status | Notes |
| Counter | Rurik and Wes | Complete | ||
| Mux | Multiplexer | Rurik and Wes | In Dev | |
| Slice | Wes | In Dev | ||
| Bit Shift | Wes | In Dev | ||
| Adder | Kaushal | In Dev | ||
| Demux | Demultiplexer | Kaushal | In Dev | |
| Multiplier | Kaushal | In Dev | ||
| Delay | Wes | In Dev | ||
| BRAM | Wes | In Dev | ||
| FIFO | Wes | In Dev | ||
DSP Blockset
The DSP Blockset will need to be rewritten using the library of python wrapped primitives. This should be a primarily python task, so any designer of these blocks will not need to know an HDL language.
DSP Modules
| Module | Description | Developer/s | Status | Notes |
| FFT | Not Yet Started | |||
| PFB | Not Yet Started | |||
| Decimator | Wes | In Dev | ||
Controllers
Each of the existing controller blocks (Verilog) will be wrapped in python (MyHDL) and can be given simulation logic. This will enable the controllers to be pulled into a design with the call of a python function.
Controller Modules
| Module | Description | Developer/s | Status | Notes |
| Software Reg | Wes | In Dev | ||
| WB/EPB Bridge | Wes | In dev | ||
| iADC | Not Yet Started | |||
| katADC | Wes | In Dev | ||
| DDR3 | Not Yet Started | |||
| GPIOs | Not Yet Started | |||
| 1GE | Not Yet Started | |||
| TGE - CX4 | Not Yet Started | |||
| TGE - SFP | Not Yet Started | |||
ROACH2 Base Modules
| Module | Description | Developer/s | Status | Notes |
| clk_gen | Clock Generation | Wes | Complete | |
| epb_infrastructure | EPB Bus infrastructure | Wes | Complete | |
| epb_wb_bridge_reg | EPB Wishbone Bridge | Wes | Complete | |
| infrastructure | Wes | Complete | ||
| sys_block | system Block | Wes | Complete | |
| wbs_arbiter | Wishbone Slave Arbiter | Wes | Complete | |