Feature_Requests_and_bugs - david-macmahon/wiki_convert_test GitHub Wiki

design rule checks for clock sources and yellow block need to be implemented. ie ADC0 clock with only an ADC in slot 1.
One directory for pcores. Specifying the platform within the pcore. Possibly only display blocks for that are available on the selected platform.
Yellow blocks to have knowledge about the platform. And display on the options on that platform. ie GPIO block.
Split up the EDK steps so that a partial run of the EDK tools is possible.
Interrupt based sw regesters.
Structure of the libraries. ie put all the ADCs in the ADC directory.
What the hell is the "found binary search"??
Demux blocks need to be consolidated and parameterise.
General blocks need to be consolidated and parameterise.
One ADC block with dropdown list of ADCs
Remove old blocks ie sw reg old and pos/neg edge blocks
Setup casper xps so that it releases matlab once the xsg is finished (Maybe spawn a new process). So that the design can be edited while the compile is running.
If you use ext_ports to add a port but get the name wrong (eg. use 'ROACH.zdok' rather than 'ROACH.zdok0') there is no error catch, the toolflow just doesn't bother to add anything to system.ucf.