Compilation_Stages - david-macmahon/wiki_convert_test GitHub Wiki

Overview

Simulink model goes in; borph executable comes out.

Compilation Stages

System Generation

  • input: Simulink Model (.mdl)
  • output: vhdl + coregen blocks

Synthesis

  • input: vhdl + coregen blocks
  • output: netlist of logic equations (.ngc)

An NGC file is a binary Xilinx implementation netlist and contains both logical design data and constraints.

NGD Build

  • input: netlist of logic equations (.ngc)
  • output: netlist of Xilinx primitives (.ngd)

An NGD (Native Generic Database) file is a logical description of the design that can be mapped into a targeted Xilinx FPGA device family.

Map

  • input: netlist of Xilinx primitives (.ngd)
  • output: mapped NCD file (.ncd & .pcf)

An NCD (Native Circuit Description) file is a physical representation of the design mapped to the components of the internal FPGA architecture.

Map takes in an NGD design description file and produces a mapped (but not routed) NCD file.

The toolflow runs a preliminary first-pass timing analysis after mapping.

PAR

  • input: mapped NCD file (.ncd & .pcf)
  • output: routed NCD file (.ncd)

PAR takes in a mapped (but not routed) NCD file and produces a fully routed NCD file.

The toolflow runs a thorough second-pass timing analysis after placement but before routing.

BitGen

  • input: routed NCD file (.ncd)
  • output: bitstream (.bit)

A BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, as well as device-specific information from other files associated with the target device.

BitGen takes in a fully routed NCD file and produces a device configuration bitstream.

Mkbof

  • input: bitstream (.bit)
  • output: BORPH Object File (.bof)

References