Clocking_Options - david-macmahon/wiki_convert_test GitHub Wiki
Most CASPER boards try to use the following convention for FPGA clocking
options, as available through the CASPER XPS
tooflow:
sys_clk
sys_clk is a fixed 100MHz clock generated by an on-board oscillator. On BEE2s and IBOBs, it is the clock used for the PLB/OPB buses and generating the PowerPC clock.
- Available on: BEE2, IBOB, ROACH
sys_clk2x
sys_clk2x is a fixed 200MHz generated by doubling sys_clk in a DCM.
- Available on: BEE2, IBOB, ROACH
usr_clk
usr_clk is a user-provided external clock.
On IBOB boards, usr_clk can be brought in through any GPIO pin, although it is recommended that SMA<0> or SMA<1> be used so that the global clock buffers on the FPGA can be accessed.
On BEE2 boards, an external usr_clk is brought in through SMA connector J117, if jumper J1000 is installed. Otherwise, it will use the on-board programmable clock generator U5 (an ICS307-02). U5 defaults to an output of 25MHz, and can be programmed using the I2C bus on the board. At this time, no BORPH/Linux drivers are available for programming the generator; this capability is only available in the BEE2 Test Suite.
- Available on: BEE2, IBOB
usr_clk2x
usr_clk2x is generated by doubling the user-provided usr_clk in a DCM.
- Available on: BEE2, IBOB
arb_clk
arb_clk is a user-programmable clock of nearly-arbitrary frequency. It uses the frequency synthesis capability of an FPGA DCM to generate a clock using an integer multiplier M (between 2 and 33) and divisor D (between 1 and 32) with the 100MHz sys_clk as reference.
- Available on: ROACH
aux0_clk
aux0_clk is a user-provided external clock.
On ROACH boards, aux0_clk should be connected to SMA connector J12.
- Available on: ROACH
aux1_clk
aux1_clk is a user-provided external clock.
On ROACH boards, aux1_clk should be connected to SMA connector J13.
- Available on: ROACH
adc0_clk
adc0_clk is the standard name for a clock provided by a daughter card plugged into connector ZDOK0. The provision for supplying this clock on global net name adc0_clk is left up to the interface designer.
- Available on: IBOB, ROACH
- Using boards: ADC2x1000-8, ADC1x3000-8, ADC4x250-8
adc1_clk
adc1_clk is the standard name for a clock provided by a daughter card plugged into connector ZDOK1. The provision for supplying this clock on global net name adc1_clk is left up to the interface designer.
- Available on: IBOB, ROACH
- Using boards: ADC2x1000-8, ADC1x3000-8, ADC4x250-8
dac0_clk
dac0_clk is the standard name for a clock provided by a daughter card plugged into connector ZDOK0. The provision for supplying this clock on global net name dac0_clk is left up to the interface designer.
- Available on: IBOB
- Using boards: DAC2x1000-16
dac1_clk
dac1_clk is the standard name for a clock provided by a daughter card plugged into connector ZDOK1. The provision for supplying this clock on global net name dac1_clk is left up to the interface designer.
- Available on: IBOB
- Using boards: DAC2x1000-16