CASPER_XPS - david-macmahon/wiki_convert_test GitHub Wiki

When you run casper_xps from the Matlab window, it spawns the CASPER XPS a dialog box with the following options:

ISE Design Flow Choice:
[ ] Update Design
[ ] Design Rules Check
[ ] Xilinx System Generator
[ ] Copy base package
[ ] IP Creation
[ ] IP Synthesis
[ ] IP Elaboration
[ ] Software generation
[ ] EDK/ISE/Bitgen

The dialog box is defined in $MLIB_ROOT/xps_library/casper_xps.m, and each check box has a corresponding callback function in $MLIB_ROOT/xps_library/gen_xps_files.m.

This page describes the action(s) that each check box triggers.

Stages

Update Design

Redraws any blocks whose parameters have changed as a result of commands in the Matlab window.

Block Object Creation

Note: This step is not optional. Hence, no checkbox.

Generates a Matlab object corresponding to each XPS block in the Simulink model.

Design Rules Check

Checks that all blocks are receiving the correct data types.

Xilinx System Generator

Runs the SysGen code generator. This takes the Simulink model and generates corresponding HDL code.

Copy base package

Copies a clean base system directory (XPS_*_base) into the current project directory.

IP Creation

Generates EDK pcores for any user-specified custom IP blocks.

IP Synthesis

Creates a custom system.mhs file based on any "yellow blocks". Also creates core_info.m and core_info.tab.

IP Elaboration

Does nothing. $MLIB_BASE/xps_library/@xps_block/elaborate.m is empty.

Software generation

To be documented.

EDK/ISE/Bitgen

To be documented.

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