CASPER_Simulink_Style_Guide - david-macmahon/wiki_convert_test GitHub Wiki

As a guide to help you build neat designs that are readable by others, here are a few tips:

General guidelines

  • Block size should be a general indication of complexity/importance of function (ie, size blocks so that bigger blocks do more complicated things).
  • Blocks performing the same function should be of uniform size.
  • Blocks incurring delays should be aligned vertically and be of uniform size.
  • If the function of the block is clear from its graphic, hide the name (eg cast, slice, relational, constant, logical, registers, delays, muxes etc).
  • Cast, Slice, and Constant blocks should all be made as small as possible while still being able to see their contents.
  • Try to keep 90deg bends in lines down to a minimum (ie, size blocks so that connecting lines can be straight as far as possible).
  • Parallel lines should never lie on top of each other.
  • Where lines meet, they should either cross at 90deg, or have a black dot to indicate a connection. These black dots have a tendency to wander... try to keep them at the meeting point.
  • If lines would cross excessively, consider using "From" and "Goto" blocks. These should always have their names hidden.
  • Debugging signals and signal taps should be kept out of the main signal flow path.
  • Add terminators to unconnected output ports to prevent extraneous warnings.

Yellow block suggestions

Yellow blocks represent interfaces to the outside world.

  • Yellow blocks' names should be kept short and not contain spaces.
  • If sensible, keep yellow blocks on the top level of the design. This way, when you open the design, you can clearly see the input and output and all the control points. This might not be feasible in very large designs.

Example

Consider the following example: Simulink_example.png

  • Notice how the delays' and counter's names are hidden to neaten the diagram, and yet no information has been lost.
  • All the delays are aligned under the counter. It is immediately obvious that these are here to account for the delay through the counter block and to ensure that the signals are always aligned.
  • 'pack0' is much larger than 'xeng_label0', so it is clear that 'pack0' performs a more complicated role.
  • The snap block is out of the signal flow.
  • 'From' blocks were used to prevent excessive routing all over the diagram.
  • Where lines cross, there are no black dots. Where lines join, there are black dots. It is clear which lines are connected and which lines aren't.