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Signal Processing Blocks

[[Adder_tree
[[Barrel_switcher
[[Bit_reverse
[[CIC_parallel
[[Cmult_4bit_br*
[[Cmult_4bit_br
[[Cmult_4bit_em*
[[Cmult_4bit_em
[[Cmult_4bit_sl*
[[Cmult_4bit_sl
[[Complex_addsub
[[C_to_ri
[[Dds
[[Dec_fir
[[Delay_bram_en_plus
[[Delay_bram_prog
[[Delay_bram
[[Delay_complex
[[Delay_slr
[[Delay_wideband_prog
[[Dram_vacc
[[Dram_vacc_tvg
[[Edge
[[Fft_biplex_real_2x
[[Fft_biplex_real_4x
[[Fft
[[Fft_wideband_real
[[Finedelay_fstop_prog
[[Finedelay_fstop_prog_cordic
[[Fir_col
[[Fir_dbl_col
[[Fir_tap
[[Freeze_cntr
[[Lo_const
[[Lo_osc
[[Mixer
[[Negedge
[[Partial_delay
[[Pfb_fir_real
[[Pfb_fir
[[Posedge
[[Power
[[Pulse_ext
[[Rcmult
[[Reorder
[[Ri_to_c
[[Square_transposer
[[Stopwatch
[[Sync_delay_en
[[Sync_delay_prog
[[Sync_gen
[[Win_x_engine
[[Xeng_tvg

Communication Blocks

[[Ten_GbE
[[Ten_GbE_v2
[[XAUI

System Blocks

[[Adc
[[x64_adc
[[Dac
[[Dram
[[GPIO
[[Qdr
[[Snapshot
[[Snap
[[Snap64
[[Software_register
[[Sram
[[XSG_core_config
[[adc083000
[[Gaussian_Random_Number_Gen
[[Correlation_Control_Block