ADC_operation - david-macmahon/wiki_convert_test GitHub Wiki

HMCAD1511 is the technical name for the ADC chip that SNAP board uses.

HMCAD1511 samples the analog signal at maximum 900 Msps. It outputs 8 bits for every sample.

Interleaving:

ADC chips achieve their high speeds through a process called interleaving as demonstrated in the diagram below (the samples are taken on the rising edges) . Channels (and lanes) take turn taking samples. The more channels the ADC chips have, the higher the maximum sampling rate.

It’s important to realize that all channels ( and their lanes) take samples no matter which demux mode you select. Demux mode is related to the number of signals you’re putting into the ADC chip. If you’re putting in only one signal, then you should select demux by four ( which tells ADC to take the input signal and interleave it between the four available channels). If you’re putting in two signals then demux by two should be selected and if you’re putting in four signals then demux by 1 should be selected (which tells the ADC to feed the signals directly to their respective channels).

So let’s say you have an antenna with two polarization so you want to input two signals into your ADC. There are four channels in the ADC, which means you can use the spare two channels to interleave with in order to increase the sampling speed. HMCAD1511 has a **theoretical** maximum sampling rate of 1Gsps. Since there are 4 channels in HMCAD1511, 1000 Msps/4 = 250 Msps is the maximum sampling rate of each lane. Interleaving with another channels brings this up to 500 Msps. So in the scenario where you have two signals going in, you can interleave each one with respective spare channel and achieve a sampling rate of 500 Msps. Taking into account the Nyquist sampling criterium, this sampling rate gives you the ability to sample a maximum frequency of 250 MHz. In this scenario you’ll use demux by 2 mode and call it a day.

Let’s go through a four signal input case. You have four channels, each has an input going into it so you can’t interleave with anything. Each channel will sample at 250 Msps, giving you the ability to input four 125MHz signals. You would use demux by 1 for this setup.

If you have only a single input then you can interleave all channels: 250Msps*4 gives you 1Gsps (theoretical! Max clock input into ADC is about 990MHz) and a 500MHz maximum signal input. This is demux by 4 mode aka distribute the input to 4 channels for interleaving.

Important calibration notes regarding demux modes: Selecting the right demux mode is vital to calibration success. Say you’re about to calibrate the ADC chips and just have the clocking signal plugged in( which you absolutely have to do because the calibration using test patterns depends on the input clock), what demux mode should you pass to the adc16_init.py script? Well, depends on how many inputs your design will have. My test design has two signals going in, which means that I have the ability to sample at 500MHz and have available signal bandwidth of 250MHz.