ADC4x250 8 - david-macmahon/wiki_convert_test GitHub Wiki

Also known as

QuadADC, QuADC

Specifications

• ADC
  • 4x Analog Devices AD9480ASUZ-250 8-bit 250Msps ADCs

• Inputs
  • Clock: 24-250MHz 50Ohm 0dBm
  • Signal:
  • Sync: LVTTL level into 50ohm load
• Outputs
  • 1x Tyco Z-DOK+ 40 differential pair connector
    • 4x 8-bit 2's complement data
    • 2x digital clocks to CASPER standard Z-DOK clock pins
    • 2x digital clocks to Z-DOK I/O pins

• Control/Config
  • AD9480 S1 multilevel logic configuration pin

• Miscellaneous
  • 3.3V, 5V supply headers
  • 6x single-ended GPIO (differential routing on host board)

• Pre-production Schematics
  • v1.0 Schematics (PDF)
  • v2.0 Schematics (PDF)

• production Schematics
  • Production Schematics (PDF)

• Pre-production Layout (Viewing Cadence Allegro BRD Files)
  • v1.0 Layout (BRD)
  • v2.0 Layout (PDF)

• production Layout (Viewing Cadence Allegro BRD Files)
  • Production fab and assembly files (zip)

• '''Test results

  • ADC rms counts vs dBm (pdf)

  • Agilent 8722ES analog input S11 vector network analyzer measurements JPG and CSV (tar)

    • tests were performed 2012sep15 on a quadADC connected to the ZDoK 0 port of a powered up Roach1 host.
    • The board happened to be clocked at 200 MHz at 0dBm and a 1PPS signal was input to the sync SMA.
    • The ZDok 1 connector was unpopulated.
    • The Roach1's FPGA was programmed with a small design that just filled a Block RAM with raw ADC samples.