ADC1x5000 8 - david-macmahon/wiki_convert_test GitHub Wiki

5Gadc_dmux12_small.jpg 5Gadc_dmux11_small.jpg

Yellow Blocks

Gateware is pushed to:

https://github.com/sma-wideband/mlib_devel

Software

Some basic calibration and testing code:

https://github.com/sma-wideband/adc_tests

Also known as

ASIAA 5Gsps ADC

Note on hardware versions

Feature Support Matrix
Platform
Version
Active yellow-block development?
Max. Sample Rate (GSps)
Bit width (bits)

There are two hardware versions of this ADC PCB available, which are designated DMUX 1:1 and DMUX 1:2 as labeled on the board silkscreen.

The DMUX 1:1 version converts to 8-bit samples The DMUX 1:2 version converts to 4-bit samples At a given ADC conversion rate, the data rate across the Z-DOK LVDS for the DMUX 1:1 is twice that for the DMUX 1:2.

The boards are loaded with the same parts (BOM same for each version except for the part number of the raw PCB). The difference between the versions is the routing of the PCB data traces. There is a demux mode setting in the ADC chip which needs to be set appropriately for the particular version being used.

The DMUX 1:1 version brings out 8 data bits per core per sample, across 32 Z-DOK pairs. When sampling at 5 GS/s the data rate across each pair is 1.25 Gb/s. The DMUX 1:2 version brings out only 4 data bits per core per pair, which each core's data demuxed by a factor of 2. Thus when sampling at 5 GS/s, each pair runs at 0.6125 Gb/s.

Applications: ROACH 2 can support the DMUX 1:1 version of the board running at full 5 GS/s rate and producing 8-bit data. Due to clocking limitations, ROACH 1 cannot support DMUX 1:1 running at full rate, on paper. According to specification for standard speed grade Virtex 5, the sampling rate on ROACH 1 is limited to 3.6 GS/s (0.9 Gb/s on each Z-DOK pair).

The DMUX 1:2 version of the ADC can run at full 5 GS/s rate on either ROACH 1 or ROACH 2.

Specifications

  • ADC
    • 1x 8-bit Single 5.0 GSPS ADC (Datasheet: File:Ev8aq160.pdf)
    • 2x 8-bit dual 2.5GSPS in two-channel mode.
    • 4x four-channel mode in the ADC IC is not supported (no connectors to deliver the analog signals).
  • Inputs
    • Clock: 2.5GHz (Max) 50Ohm 0dBm into SMA socket
    • Signals: each is single-ended into SMA socket
    • Sync: LVTTL, 5V tolerant, terminated with 50 ohm load, into SMA socket
  • Outputs
    • 1x Tyco Z-DOK+ 40 differential pair connector
      • For non-demux version : 4x 8-bit offset binary data @ DDR
      • '''For demux version : 8x 4-bit offset binary data @ DDR '''
      • 1x digital clock to CASPER standard Z-DOK clock pins
  • Control/Configuration
    • ADC: SPI 3-wire Serial
    • External SPI interface on board for future development.
  • Printed Circuit Board
    • Stack Up
      • 4-layers
    • Thickness
      • ?? mm
    • Material

      • Rogers RO4003 on top anf bottom

      • FR-4 in between 2 layers.

    • Insertion Loss
      • ??
    • Z Variation (50Ω nom.)
      • ??
  • Miscellaneous

    • Passive heatsink

Versions

  • V2.0 - Production Version

** Schematics non-demux (PDF)

** Schematics Demux 1:2 (PDF)

** PCB Manufacturing Data Non-demux (gzip)

** PCB Manufacturing Data Demux 1:2 (gzip)

** Design Files Non-demux (gzipped orcad)

** Design Files Demux 1:2 (gzipped orcad)

** Bill Of Materials (xls)

**

There is a bug on the silk screen that R104 and R105 are wrong. The one close to U2 is R104, the other is R105. Normally, the R104 should be unpopulated, and R105 should be installed with 0 ohm.

Measured Performance (Preliminary)

  • Input RF Bandwidth
    • 1MHz - 1800MHz for non-demux version on Virtex 5 speed grade 1 chip with clock domain crossing scheme applied.
    • 1MHz - 2000MHz for demux version on Virtex 5 speed grade 1 chip.
  • Sampling Frequency
    • 1.8GHz for non-demux version.
    • 2.0GHz for demux version.
  • VSWR
    • ??
      • 0dB attenuation in signal path
  • Channel-to-Channel Crosstalk
    • ??
      • full-scale input
  • SFDR

    • 4 bits version, please see memo 43

  • Passband Flatness

  • Passband Ripple

  • ENOB
    • 4 bits version, please see memo 43
  • SNR
    • 4 bits version, please see memo 43

NRAO Characterization for VEGAS

ADC Characterization by NRAO (PDF) March 2012

CfA Characterization for SMA

Characterizing the Performance of a High-speed ADC for the SMA Digital Backend (JAI) March 2014

SMA Wideband Twiki

Please refer to the following link for additional test results on these ADCs:

https://www.cfa.harvard.edu/twiki/bin/view/SMAwideband/AnalogToDigital