Flareon Instruction Format

structure

|31    25|24   20|19   15|14     12|11   7|6      0|
| funct7 |  rs2  |  rs1  |  funct  |  rd  | opcode |

imm_sham = [24:20]
imm_i    = [31:20]
imm_s    = [31:25] + [11:7]
imm_u    = [31:12] << 12
imm_b    = ([31] + [7] + [30:25] + [11:8]) << 1
imm_j    = ([31] + [19:12] + [20] + [30:21]) << 1

opcode

OP_IMM   = 0010011
OP_OP    = 0110011
BRANCH   = 1100011
OP_JALR  = 1100111
OP_AUIPC = 0010111
OP_LUI   = 0110111
OP_LOAD  = 0000011
LOAD_FP  = 0000111
OP_STORE = 0100011
STORE_FP = 0100111
OP_FP    = 1010011
OP_INOUT = 1111111

• OP_IMM

| name | funct |            meaning              |
| addi |  000  | reg[rd] = reg[rs1] + imm_i      |
| slli |  001  | reg[rd] = reg[rs1] << imm_sham  |
| xori |  100  | reg[rd] = reg[rs1] ^ imm_i      |
| srai |  101  | reg[rd] = reg[rs1] >>> imm_sham |
| andi |  111  | reg[rd] = reg[rs1] & imm_i      |

• OP_LUI

| name |     meaning     |
| lui  | reg[rd] = imm_u |

• OP_AUIPC

| name  |       meaning        |
| auipc | reg[rd] = pc + imm_u |

• OP_JALR

| name |               meaning                   |
| jalr | reg[rd] = pc + 4; pc = reg[rs1] + imm_i | 

• OP_BRANCH

| name  | funct |                  meaning                     |
| beq   |  000  | pc = pc + (reg[rs1] == reg[rs2] ? imm_b : 4) |
| bne   |  001  | pc = pc + (reg[rs1] != reg[rs2] ? imm_b : 4) |
| blt   |  100  | pc = pc + (reg[rs1] < reg[rs2] ? imm_b : 4)  |
| bge   |  101  | pc = pc + (reg[rs1] >= reg[rs2] ? imm_b : 4) |
| beqi  |  010  | pc = pc + (reg[rs1] == imm_sham ? imm_b : 4) |
| bnei  |  011  | pc = pc + (reg[rs1] != imm_sham ? imm_b : 4) |
| blti  |  110  | pc = pc + (reg[rs1] < imm_sham ? imm_b : 4)  |
| bgti  |  111  | pc = pc + (reg[rs1] > imm_sham ? imm_b : 4) |  (not bgei)

• OP_LOAD

| name |              meaning            |
|  lw  | reg[rd] = mem[reg[rs1] + imm_i] |

• OP_STORE

| name |              meaning             |
|  sw  | mem[reg[rs1] + imm_s] = reg[rs2] |

• OP_OP

| name | funct |            meaning            |
| add  |  000  | reg[rd] = reg[rs1] + reg[rs2] |
| sub  |  010  | reg[rd] = reg[rs1] - reg[rs2] |
| xor  |  100  | reg[rd] = reg[rs1] ^ reg[rs2] |

• LOAD_FP

| name |              meaning             |
| flw  | freg[rd] = mem[reg[rs1] + imm_i] |

• OP_STORE

| name |              meaning              |
| fsw  | mem[reg[rs1] + imm_s] = freg[rs2] |

• OP_FP

| name  | funct7   |              meaning              |
| fadd  | 0000000  | freg[rd] = freg[rs1] + freg[rs2]  |
| fsub  | 0000100  | freg[rd] = freg[rs1] - freg[rs2]  |
| fmul  | 0001000  | freg[rd] = freg[rs1] * freg[rs2]  |
| fdiv  | 0001100  | freg[rd] = freg[rs1] / freg[rs2]  |
| fsqrt | 0101100  | freg[rd] = sqrt(freg[rs1])        |
| feq   | 1010010  | freg[rd] = freg[rs1] == freg[rs2] |
| flt   | 1010001  | freg[rd] = freg[rs1] < freg[rs2]  |
| fle   | 1010000  | freg[rd] = freg[rs1] <= freg[rs2] |
| fmv   | 0010000  | freg[rd] = freg[rs1]              |
| fneg  | 0010001  | freg[rd] = -1 * freg[rs1]         |
| fabs  | 0010010  | freg[rd] = abs(freg[rs1])         |
| finv  | 0010011  | freg[rd] = inverse(freg[rs1])     |

• OP_INOUT

| name  | funct |        meaning       |
| write |  000  | write(reg[rs1][7:0]) |  
| read  |  001  | read(reg[rd1][7:0])  |