flareon ISA

from RV32-I

addi, xori など末尾にiがついている命令では、レジスタの値と即値の間での演算を行う。 命令形式などの詳細はRISC-Vのスペックまたはこの記事を参照。

mnemo	meaning
lui	load upper immediate
auipc	add upper immediate to pc
jalr	jump and link register
lw	load word
sw	store word
beq	branch if equal
bne	branch if not equal
blt	branch if less than
bge	branch is greater than or equal
add/addi	addition
xor/xori	xor
sub	subtraction
slli	left logical shift
srai	right arithmetic shift

extended instruction for integer register

RV32Iにはないオリジナルの整数レジスタ用命令

mnemo	命令形式	補足など
beqi	beqi rs, imm, label	branch if equal immediate
bnei	bnei rs, imm, label	branch if not equal immediate
blti	blti rs, imm, label	branch if less than immediate
bgti	bgti rs, imm, label	branch if greater than immediate
w	w rs	rsの内容の下位8bitをuartに送信する
r	r rd	uartから受信した8bitをrdに入れる

Floating Point

mnemo	命令形式	補足など
flw	flw frd, offset(rs)
fsw	fsw frs, offset(rd)
fadd	fadd frd, frs1, frs2
fsub	fsub frd, frs1, frs2
fmul	fmul frd, frs1, frs2
fdiv	fdiv frd, frs1, frs2
fsqrt	fsqrt frd, frs
feq	feq rd, frs1, frs2	frs1, frs2は浮動小数レジスタでrdは整数レジスタ trueの場合は1,falseの場合は0を入れる
fle	fle rd, frs1, frs2	同上
flt	flt rd, frs1, frs2	同上
fmv	fmv frd, frs
fneg	fneg frd, frs	符号反転
fabs	fabs frd, frs	レイトレで必要
finv	finv frd, frs	逆数

pseudo-instruction

RISC-V referenceから

RISC-Vの仕様のp110で定義されている。

Pseudo Instruction	Base Instruction	Meaning
la rd, symbol	auipc rd, symbol[31:12] addi rd, rd, symbol[11:0]	Load address
li rd, imm	addi rd, x0, imm or lui rd, imm[31:12] addi rd, rd, imm[11:0]	Load immediate
mv rd, rs	addi rd, rs, 0	Copy registers
neg rd, rs	sub rd, x0, rs	Two's complement
bgt rs, rt, offset	blt rt, rs, offset	Branch if greater than
ble rs, rt, offset	bge rt, rs, offset	Branch if less than
j offset	jal x0, offset	Jump Deprecated jal
jr rs	jalr x0, rs, 0	Jump register
ret	jalr x0, x1, 0	Return from subroutine
call offset	auipc x6, offset[31:12] jalr x1, x6, offset[11:0]	Call far-away subroutine
tail offset	auipc x6, offset[31:12] jalr x0, x6, offset[11:0]	Tail-call far-away subroutine

flareon original

Pseudo Instruction	Base Instruction	Meaning
b offset	bge zero, zero, offset	Branch unconditionally
lda rd, symbol	lui rd, symbol[31:12] addi rd, rd, symbol[11:0]	Load data address
fli frd, label	lui frd, label[31:12] addi frd, frd, label[11:0]	Load immediate for float
lwl rd, label(rs)	(label はアセンブル時に計算)	rd <- label + rs
swl rd, label(rs)	(label はアセンブル時に計算)	label + rs <- rd
flwl frd, label(frs)	(label はアセンブル時に計算)	frd <- label + frs
fswl frd, label(frs)	(label はアセンブル時に計算)	label + frs <- frd
lwd rd, label(imm)	(label はアセンブル時に計算)	rd <- (label + imm)
swd rd, label(imm)	(label はアセンブル時に計算)	(label + imm) <- rd
flwd frd, label(imm)	(label はアセンブル時に計算)	frd <- (label + imm)
fswd frd, label(imm)	(label はアセンブル時に計算)	(label + imm) <- frd