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APPROX diagram:

Components:

• AXI VDMA (AXI Video Direct Memory Access)
• VTC (Video Timing Controller)
• AXI4-Stream (AXI4 Stream to Video Out)

The design uses:

• AXI VDMA (AXI Video Direct Memory Access): Transfers video frames from memory to the AXI4-Stream domain.
• VTC (Video Timing Controller): Generates VGA timing signals (HSYNC, VSYNC).
• AXI4-Stream to Video Out: Converts streamed video data into parallel VGA signals.

Inputs:

• video_in
• s_axis_video_tdata[23:0]
• s_axis_video_tlast
• s_axis_video_tready
• s_axis_video_tuser
• s_axis_video_tvalid
• + vtiming_in
• aclk
• acklen
• aresetn
• fid
• vid_io_out_ce

This signal represents the primary video data input, carrying pixel information in AXI4-Stream format. It is a structured signal set used to transfer video frames from an AXI4-Stream source.

This 24-bit data bus carries the pixel color information. Typically following an RGB888 format; i.e.

• Bits [23:16] - Red component (8 bits)
• Bits [15:8] - Green component (8 bits)
• Bits [7:0] - Blue component (8 bits)

This signal marks the last pixel in a scanline (row) of the video frame. It is asserted at the end of each horizontal line to indicate the end of transmission for that row.

A flow control signal that indicates when the downstream module is ready to accept data. If tready is deasserted, the upstream source must pause data transmission.

AXI4-Stream TREADY. Inverted FIFO full

A user-defined sideband signal is used to indicate the start of a frame, ie the first pixel. It is asserted at the beginning of a new video frame (on the first pixel of the first row). The SOF signal may be asserted an arbitrary number of aclk cycles before the first pixel value is presented on tdata, as long as a tvalid is not asserted.

COMES FROM THE TIMING CONTROLLER?

EXAMPLE

For example, if a 1920x1080 resolution image is being streamed, tuser will be high for the first pixel (X=0, Y=0) and low for all other pixels in the frame.

This signal is asserted when valid video data is present on the s_axis_video_tdata bus.

The SOF signal may be asserted an arbitrary number of aclk cycles before the first pixel value is presented on tdata, as long as a tvalid is not asserted.

PROBS COMES FROM THE OUTPUT OF WHERE EVER tdata COMES FROM

Represents incoming video timing signals that help synchronize video processing. This includes horizontal and vertical synchronization pulses and active video region indicators.

MOST DEFINITELY COMES FROM THE OUTPUT OF THE TIMING CONTROLLER

An acknowledgment signal that confirms reception of control signals or commands, ensuring synchronization between processing blocks.

THIS WILL LIKELY GO BACK TO THE INPUT OF THE TIMING CONTROLLER (either det_clken or gen_clken or clken)

Acknowledgment enable signal, controlling whether the any signals besides ARESETn should be used.

Setting ACLKEN Low (deasserted) halts the operation of the AXI4-Stream Bus despite rising edges on the ACLK pin. When ACLKEN is deasserted, core AXI4-Stream inputs are not sampled, except ARESETn, which supersedes ACLKEN.

The ACLKEN pin facilitates:

• Multi-cycle path designs (high speed clock division without clock gating)
• Standby operation of subsystems to save on power
• Hardware controlled bring-up of system components

THIS WILL LIKELY GO BACK TO THE INPUT OF THE TIMING CONTROLLER (either det_clken or gen_clken or clken)

Active-low ACLK synchronous reset signal used to initialize or reset the module. When aresetn is low, the module is held in reset state.

MAYBE GOES BACK TO TIMING CONTROLLER resetn In general, the core does not need to be reset during normal operation. The core will continuously and automatically attempt to lock the video output to the incoming AXI4-video stream until successful. The state machine in the output synchronizer block

When the core is in common clock mode (I think what we are going to use as we are doing master), there is only a single reset input port aresetn that is used to reset both the AXI4-Stream output and Video input sides of the bridge

ONLY FOR INTERLACED VIDEO

It should be connected to the field-ID bit of the next device downstream that is field-aware, otherwise it should be left unconnected or driven to ground.

Frame Identification signal used to distinguish between odd and even frames in interlaced video formats. It helps maintain correct field sequencing in progressive and interlaced video applications.

Clock enable signal for video output. This signal ensures proper clocking and timing synchronization between video processing blocks.

MOST DEFINITELY COMES FROM THE OUTPUT OF THE TIMING CONTROLLER

These inputs signals control the raster scan behavior of a VGA monitor.

What is a raster scan?

A raster scan is the systematic pattern in which an electron beam moves across a CRT (cathode-ray tube) display to create an image, moving horizontally from left to right to draw each line, then quickly returning to the left edge (horizontal retrace) before moving down slightly to start the next line. When it reaches the bottom of the screen, the beam returns to the top (vertical retrace) to begin the next frame. In VGA monitors, this scanning pattern is controlled by synchronization signals (hsync and vsync) that coordinate the timing of these beam movements to ensure proper image formation.

• vid_io_out
• vtg_ce
• locked
• overflow
• underflow
• fifo_read_level[10:0]
• write[31:0]

VTC clock enable. Used to halt the timing generator for synchronization purposes.

If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the LOCKED port.

MAYBE this is like a mutex.

Flag saying the FIFO has over-flowed. Synchronous to vid_io_in_clk

Flag saying the FIFO has under-flowed. (SHOULD NEVER OCCUR)

Status flag used to monitor synchronizer state machine transitions and VTG lag. Anytime the synchronizer state changes the state transition is captured in the status flag. The state transition bits are sticky and cleared on reset. The VTG lag is a count of the number of clocks that the VTG was lagged as a result of stalls in the stream. VTG lag is updated on every vid_io_out_clk.

• status[0] – Idle state
• status[1] – Course Align, Wait for VTG SOF
• status[2] – Course Align, Wait for FIFO SOF
• status[3] – Fine Align, VTG EOL Leading
• status[4] – Fine Align, VTG EOL Lagging
• status[5] – Fine Align, VTG SOF Leading
• status[6] – Fine Align, VTG SOF Lagging
• status[7] – Fine Align Active
• status[8] – Fine Align Locked
• status[9] – Lost Align, VTG EOL Leading
• status[10] – Lost Align, VTG EOL Lagging
• status[11] – Lost Align, VTG SOF Leading
• status[12] – Lost Align, VTG SOF Lagging
• status[31:16] – VTG Lag

The AXI4-Stream to Video Out core receives video through the AXI4-Stream slave interface defined in the _Video IP:

Signal Name	Direction	Width Description
vid_active_video	Out	1	Video output data valid. 1 = active video, 0 = blanked video
vid_vsync	Out	1	Video output vertical sync. Active HIGH
vid_hsync	Out	1	Video output horizontal sync. Active HIGH
vid_vblank	Out	1	Video output vertical blank. Active HIGH
vid_hblank	Out	1	Video output horizontal blank. Active HIGH
vid_data	Out	8-256	Parallel video output data. Active HIGH
vid_field_id	Out	1	Video field. 0= even field, 1= odd field. Synchronous to vid_out_in_clk.

Signal Name	Direction	Width	Description
vtg_vsync	In	1	VTC vertical sync. Active High
vtg_hsync	In	1	VTC horizontal sync. Active High
vtg_vblank	In	1	VTC vertical blank. Active High
vtg_hblank	In	1	VTC horizontal blank. Active High
vtg_act_vid	In	1	VTC active video signal. 1 = active video, 0 = blanked video
vtg_field_id	In	1	VTC field ID. Used only for interlace. 0= even field, 1= odd field. Tie LOW for non-interlace operation.

Table below describes the AXI4-Stream signal names and descriptions. See AXI4-Stream Video IP and System Design Guide.

Table 2‐4: AXI4-Stream Data Interface Signal Descriptions

Signal Name	Direction	Width	Description
s_axis_video_tvalid	Input	1	AXI4-Stream TVALID. Active video data enable
s_axis_video_tuser	Input	1	AXI4-Stream TUSER. Start of Frame
s_axis_video_tlast	Input	1	AXI4-Stream TLAST. End of Line
s_axis_video_tready	Output	1	AXI4-Stream TREADY. Inverted FIFO full

Table 2‐2: Port Name I/O Width Description

IMPORTANT: All timing control signals are required for the proper operation of the AXI4-Stream to Video Out core. The only exception is vtg_field_id which is not required for non-interlace operation. Although all syncs and blanks may not be required at the video output, they are all required for the correct internal operation of the AXI4-Stream to Video Out core.

For 640×480 @ 60Hz VGA, the required timing is:

Parameter	Pixels	Time (µs)	Clock Cycles (@ 25MHz pixel clock)
Horizontal Sync (HSYNC)	800	32	800
Active Video	640	25.6	640
Front Porch	16	0.64	16
Sync Pulse	96	3.84	96
Back Porch	48	1.92	48
Vertical Sync (VSYNC)	525 lines	16.7ms	525
Active Video	480	15.36ms	480
Front Porch	10	320µs	10
Sync Pulse	2	64µs	2
Back Porch	33	928µs	33

• Mode: Memory-to-Stream (MM2S)
• Frame Buffer: Located in DDR or BRAM.
• Width & Height: Set to 640×480.
• Pixel Format: 8-bit per pixel (RGB332).

• Mode: Master mode (Generates VGA sync signals).
• Timing Configuration: Matches VGA 640×480 @ 60Hz.
• Outputs:
  • h_sync → HSYNC (Active low)
  • v_sync → VSYNC (Active low)
  • video_active → High when pixels are valid.

• Input: Streamed data from AXI VDMA.
• Output: Parallel RGB signals + HSYNC & VSYNC.
• FIFO Configuration: Prevents underflows.
• Clocking:
  • Pixel Clock: 25MHz (generated using a PLL).
  • Video Clock: Matches pixel clock.

1. AXI VDMA (Memory to Stream)

   • MM2S AXI-Stream Output → AXI4-Stream to Video Out Input
   • AXI Master Bus → External Memory (DDR/BRAM)
   • Clock: AXI Clock (100MHz)
   • Reset: System Reset

2. Video Timing Controller (VTC)

   • Clock: 25MHz Pixel Clock
   • Sync Outputs: Connected to AXI4-Stream to Video Out
   • Mode: Master mode

3. AXI4-Stream to Video Out

   • AXI4-Stream Input: From AXI VDMA
   • Timing Inputs: From VTC
   • Parallel RGB Output: Directly drives VGA signals
   • Sync Signals: From VTC

• Ensure HSYNC and VSYNC match VGA timing.
• Monitor AXI4-Stream Data using ILA in Vivado.
• Check FIFO Buffer Status in AXI4-Stream to Video Out.

• Increase FIFO depth in AXI4-Stream to Video Out.
• Ensure VDMA MM2S is fetching frames at the right rate.

Signal Name	Direction	Width	Description
vtg_vsync	In	1	VTC vertical sync. Active High
vtg_hsync	In	1	VTC horizontal sync. Active High
vtg_vblank	In	1	VTC vertical blank. Active High
vtg_hblank	In	1	VTC horizontal blank. Active High
vtg_act_vid	In	1	VTC active video signal. 1 = active video, 0 = blanked video
vtg_field_id	In	1	VTC field ID. Used only for interlace. 0= even field, 1= odd field. Tie LOW for non-interlace operation.