PG016 October 4, 2017

The Xilinx LogiCORE™ IP Video Timing Controller core is a general purpose video timing generator and detector. The core is highly programmable through a comprehensive register set allowing control of various timing generation parameters. This programmability is coupled with a comprehensive set of interrupt bits which provides easy integration into a processor system for in-system control of the block in real-time. The Video Timing Controller is provided with an optional AXI4-Lite compliant interface.

• Support for progressive or interlaced video frame sizes up to 8192 x 8192
• Direct regeneration of output timing signals with independent timing and polarity inversion
• Automatic detection and generation of horizontal and vertical video timing signals
• Support for multiple combinations of blanking or synchronization signals
• Automatic detection of input video control signal polarities
• Support for detection and generation of horizontal delay of vertical blank/sync
• Programmable output video signal polarities
• Generation of up to 16 additional independent output frame synchronization signals
• Optional AXI4-Lite processor interface
• High number of interrupts and status registers for easy system control and integration

Provided by Xilinx at the, Inc.

• 1. For a complete listing of supported devices, see the Vivado IP Catalog.

• 2. Refer to the Video IP: AXI Feature Adoption section of AXI Reference Guide [Ref [1](#page-88-2).

• 3. Standalone driver details can be found in the SDK directory (<install_directory>/SDK//data/embeddedsw/doc/ xilinx_drivers.htm). Linux OS and driver support information is available from

• 4. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.

All video systems require management of video timing signals, which are used to synchronize processes. The Video Timing Controller serves the function of both detecting and generating these timing signals.

The input side of this core automatically detects horizontal and vertical synchronization pulses, polarity, blanking timing and active video pixels. While on the output, it generates the horizontal and vertical blanking and synchronization pulses used with a standard video system including support for programmable pulse polarity. The core is commonly used with the Video in to AXI4-Stream core to detect the format and timing of incoming video data or with the AXI4-Stream to Video out core to generate outgoing video timing for downstream sinks such as a video monitor.

Figure 1-1 shows a typical video frame including timing signals.

IMPORTANT: All signals are shown with active high polarity.

X-Ref Target - Figure 1-1

Figure 1‐1: Example Video Frame and Timing Signals

A video frame can be completely described in terms of timing by only a few definitions. A video frame comprises active video and blanking periods. The vertical and horizontal synchronization signals describe the video frame timing, which includes active and blanking data. In addition, the frame synchronization signals can be used to synchronize video data from one component to another within a video system. There are additional signals that can also be used to control the video system, such as a signal to differentiate valid chroma samples.

Video systems may utilize different combinations of blank, synchronization or active signals with various polarities to synchronize processing and control video data. The Video Timing Controller simplifies working with video timing signals by providing a highly programmable and flexible core that allows detection and generation of the various timing signals within a video system.

The Video Timing Controller core supports the AXI4-Lite interface and a constant-mode interface. The AXI4-Lite interface allows the core to be easily incorporated into a Vivado project. The Constant interface utilizes core parameters configurable by the Graphical User Interface (GUI) to setup the core for fixed-mode operation. These configurable options allow the Video Timing Controller core to be easily integrated with AXI4 based processor systems, with non-AXI4-compliant processors systems with some additional logic, and in systems without a processor.

The Video Timing Controller core supports detecting video frame sizes up to 8192 clocks by 8192 lines (including horizontal and vertical blanking). The detection typically requires three to five input video frames to detect and lock. The Video Timing Controller core automatically detects the timing involved with horizontal/vertical blanks and syncs. The timing of the active_video and the active_chroma signals are also detected. This allows the user to easily determine the video frame size via the core register (AXI4-Lite) interface. The minimum set of signals used for detection is either vertical blank, horizontal blank and active video or vertical sync, horizontal sync and active video. The polarities of each input signal is also detected and reported via the register interface to allow easy use of each signal once the polarity is known.

The core also supports generating and regenerating (matching the detected input) video frame sizes up to 8192 clocks by 8192 lines (including blanking time). The output can be the same format or a different format as the detected input. This allows detecting one format and generating a different format. The output can also be synchronized to the detected input and has separate signal polarity settings as well. This allows regenerating the input with different signal polarities or with slight timing adjustments (such as delayed or shorted active video).

The Video Timing Controller core supports up to 16 frame sync output signals. These are toggled high for one clock cycle during each frame. These frame syncs allow triggering timing critical hardware processes at different times during a frame.

• Video Surveillance
• Industrial Imaging
• Video Conferencing
• Machine Vision
• Video Systems requiring timing detection or timing generation

This Xilinx LogiCORE IP module is provided at no cost under the terms of the Xilinx Core License Agreement. The module is shipped as part of the Vivado Design Suite. For full access to all core functionalities in simulation and in hardware, you must purchase a license for the core. Contact your local Xilinx sales representative for information about pricing and availability.

For more information, visit the Video Timing Controller product web page.

Information about other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. For information on pricing and availability of other Xilinx LogiCORE IP modules and tools, contact your local Xilinx sales representative.

The Video Timing Controller core is compliant with the AXI4-Lite interconnect standards. Refer to the Video IP: AXI Feature Adoption section of the Vivado AXI Reference Guide (UG1037) [Ref [1](#page-88-2) for additional information.

The following sections detail the performance characteristics of the Video Timing Controller core.

This section contains typical clock frequencies for the target devices. The maximum achievable clock frequency can vary. The maximum achievable clock frequency and all resource counts can be affected by other tool options, additional logic in the FPGA device, using a different version of Xilinx tools and other factors. Refer to in Table 2-1 through Table 2-4 for device-specific information.

• Virtex-7, Kintex-7, Zynq-7000 (XC7Z030, XC7Z045) Devices: 225MHz
• Artix-7, Zynq-7000 (XC7Z010, XC7Z020) Devices: 150MHz

The Video Timing Controller core does not read or generate data, and therefore, does not have a specific data latency.

The Video Timing Controller core monitors and generates control signals. The output control signals can be configured to be the same as the input with no latency, or the output signals can be configured to incur a multi-clock or multi-line delay.

The Video Timing Controller core does not read or generate data, and does not have a specific throughput.

For an accurate measure of the usage of primitives, slices, and CLBs for a particular instance, check the Display Core Viewer after Generation check box in the interface.

The information presented in Table 2-1 through Table 2-4 is a guide to the resource utilization and maximum clock frequency of the Video Timing Controller core for all input/ output width combinations for Virtex-7, Kintex-7, Artix-7, and Zynq-7000 families. UltraScale™ results are expected to be similar to 7 series results. The design was tested using Vivado with default tool options for characterization data.

Table 2‐1: Virtex-7 FPGA Performance

Table 2‐1: Virtex-7 FPGA Performance (Cont'd)

Table 2‐2: Kintex-7 FPGA and Zynq-7000 Devices with Kintex Based Programmable Logic Performance

Table 2‐2: Kintex-7 FPGA and Zynq-7000 Devices with Kintex Based Programmable Logic Performance (Cont'd)

Table 2‐2: Kintex-7 FPGA and Zynq-7000 Devices with Kintex Based Programmable Logic Performance (Cont'd)

Table 2‐3: Artix-7 FPGA and Zynq-7000 Device with Artix Based Programmable Logic Performance (Cont'd)

Table 2‐4: Zynq-7000 Device Performance (Cont'd)

Table 2‐4: Zynq-7000 Device Performance (Cont'd)

This chapter provides detailed descriptions for each interface. In addition, detailed information about configuration and control registers is included.

The Video Timing Controller (VTC) core uses the AXI4-Lite industry standard control interface to connect to other system components. The following sections describe the various interfaces available with the core. Some signals are optional and not present for all configurations of the core. The AXI4-Lite interface and the IRQ pin are present only when the core is configured via the GUI with an AXI4-Lite control interface. The INTC_IF interface is present only when the core is configured via the GUI with the INTC interface enabled. Figure 2-1 illustrates an I/O diagram of the VTC core.

X-Ref Target - Figure 2-1

Figure 2‐1: TC Core Top-Level Signaling Interface

Video systems commonly use an integrated processor system to dynamically control the parameters within the system. This is especially important when several independent image processing cores are integrated into a single FPGA. The Video Timing Controller core can be configured with an AXI4-Lite interface.

The signals not included in the AXI4-Lite interface are specified in Table 2-5.

Table 2‐5: Common Port Descriptions (Cont'd)

1. All ports are little-endian.

The clk, clken and resetn, det_clken, and gen_clken signals are shared between the core and the Video Timing interfaces. The AXI4-Lite control interface has its own set of clock, clock enable and reset pins: S_AXI_ACLK, S_AXI_ACLKEN and S_AXI_ARESETn.

The Video Timing interfaces must be synchronous to the core clock signal clk. All Video Timing interface input signals are sampled on the rising edge of clk. All Video Timing output signal changes occur after the rising edge of clk. If the clk signal is not running, the AXI4-Lite interface asserts the slave error response (0x2) for all addresses. The clken pin is an active-high, synchronous clock-enable input pertaining to Video Timing interfaces. Setting clken low (de-asserted) halts the operation of the core despite rising edges on the clk pin. Internal states are maintained, and output signal levels are held until clken is asserted again. When clken is de-asserted, core inputs are not sampled, except resetn, which supersedes clken. This clock must be running for AXI4-Lite

X-Ref Target - Figure 2-2

X-Ref Target - Figure 2-3

registers to be read and/or written, since all core registers reside within the core clock domain. This clock enable must be asserted high for AXI4-Lite registers to be read and/or written, since all core registers reside within the core clock domain. If the clock enable is deasserted, the AXI4-Lite interface asserts the slave error response (0x2) for all addresses.

The det_clken pin is an Active-High, synchronous clock-enable pertaining to the Video Timing Controller detector (input) interface. This clock enable allows halting the detector independently from the generator. The internal detector clock enable is a logical "AND" between the clken and det_clken inputs. The internal logic that controls the detector sub-core clock enable is shown in Figure 2-2.

Figure 2‐2: Detector Internal Clock Enable Logic

The gen_clken pin is an Active-High, synchronous clock-enable pertaining to the Video Timing Controller generator (output) interface. This clock enable allows halting the generator independently from the detector. The internal generator clock enable is a logical "AND" between the clken and get_clken inputs. For example, to enable the detector while halting the generator, drive clken to '1', det_clken to '1' and gen_clken to '0'. The internal logic that controls the generator sub-core clock enable is shown in Figure 2-3.

Figure 2‐3: Generator Internal Clock Enable Logic

X-Ref Target - Figure 2-4

The resetn pin is an active-low, synchronous reset input pertaining to only Video Timing interfaces. resetn supersedes clken, and when set to 0, the core resets at the next rising edge of clk even if clken is de-asserted. The resetn signal must be synchronous to the clk and must be held low for a minimum of 32 clock cycles of the slowest clock. This reset must be asserted high for AXI4-Lite registers to be read and/or written, since all core registers reside within the core clock domain. If the reset is asserted low, the AXI4-Lite interface asserts the slave error response (0x2) for all addresses.

The fsync_in pin is an Active-High input. The video timing generator is synchronized to the fsync_in input if used. The fsync_in should be driven high for only one clock cycle per frame. This resets all internal generator counters and starts the generated frame timing synchronized to this input. Internally, the fsync_in pin is logically "OR" combined with the internal frame sync det_fsync, produced by the detector. The internal frame sync det_fsync is generated by the video timing detector and can be used to synchronize the generator timing to the detector timing. The internal logic for this is show in Figure 2-4. If the fsync_in input is used, then the detector must be disabled. Likewise, if the detector is used, then the fsync_in pin must be driven to '0'. The use of the external fsync_in pin and the detector can be changed at run-time but it is important that fsync_in and det_fsync are never asserted simultaneously.

Figure 2‐4: Video Timing Controller Internal fsync Logic

The AXI4-Lite interface creates a core that can be easily added to an Vivado Project as a processor peripheral. This section describes the I/O signals associated with the Video Timing Controller AXI4-Lite interface.

1. The function and timing of these signals are defined in the AMBA AXI Protocol Version: 2.0 Specification.

2. For signals S_AXI_RRESP[1:0] and S_AXI_BRESP[1:0], the core does not generate the Decode Error ('11') response. Other responses such as '00' (OKAY) and '10' (SLVERR) are generated by the core based upon certain conditions.

The AXI4-Lite Interface provides a memory mapped interface for all programmable registers within the core. All registers default to the values specified in Page 2 of the core GUI. All other bits default to 0x00000000 on Power-on/Reset unless otherwise noted.

Table 2‐7: AXI4-Lite Address Map

Table 2‐7: AXI4-Lite Address Map (Cont'd)

Table 2‐7: AXI4-Lite Address Map (Cont'd)

The DET_ENABLE bit allows enabling the detector independently from the generator. The internal detector enable is a logical "OR" between the DET_ENABLE and SW_ENABLE bits in the control register. The internal logic that controls the detector sub-core enable is shown in Figure 2-5. The SW_ENABLE bit allows setting one bit to '1' to enable both the detector and the generator. To enable the detector or the generator only, the SW_ENABLE bit must be set to '0' and the detector/generator ENABLE bits (Control Register bits [3:2]) set independently.

X-Ref Target - Figure 2-5

X-Ref Target - Figure 2-6

Figure 2‐5: Detector Internal Enable Logic

The internal generator enable is a logical "OR" between the GEN_ENABLE and SW_ENABLE bits in the control register. The internal logic that controls the generator sub-core enable is shown in Figure 2-6.

Figure 2‐6: Generator Internal Enable Logic

Note: Writing a '1' to a bit in the STATUS register will clear the corresponding interrupt when set. Writing a '1' to a bit that is cleared, will have no effect.

Table 2‐10: Error Register (Address Offset 0x0008)

Writing a '1' to a bit in the ERROR register will clear the corresponding bit when set. Writing a '1' to a bit that is cleared, will have no effect.

Table 2‐11: IRQ Enable Register (Address Offset 0x000C)

Setting a bit high in the IRQ_ENABLE register enables the corresponding interrupt. Bits that are low mask the corresponding interrupt from triggering.

Table 2‐29: Generator Polarity Register (Address Offset 0x006C)

Frame Sync 1-15 Config Registers (address offset 0x0100 - 0x013c) have the same format as the Frame Sync 0 Config Register.

Table 2‐40: Generator Global Delay Register (Address Offset 0x140) (Cont'd)

X-Ref Target - Figure 3-1

The Video Timing Controller core contains three modules: the video timing detector, the video timing generator and the interrupt controller. See Figure 3-1.

Either the detector or the generator module can be disabled at instantiation with the GUI to save resources.

Figure 3‐1: Video Timing Controller Block Diagram

X-Ref Target - Figure 3-2

The Video Timing Controller Inputs and Outputs are discussed and shown with timing diagrams in the following sections.

The blanking and active period definitions were discussed in Chapter 1, Overview. In addition to these definitions, the period from the start of blanking (or end of active video) to the start of synchronization is called the front porch. The period from the end of synchronization to the end of blanking (or start of active video) is called the back porch. The total horizontal period (including blanking and active video) can also be defined, and similarly the total vertical period.

Figure 3-2 shows the start of the horizontal front porch (Hblank Start), synchronization (Hsync Start), back porch (Hsync End) and active video (SAV). It also shows the start of the vertical front porch (Vblank Start), synchronization (Vsync Start), back porch (Vsync End) and active video (SAV). The total number of horizontal clock cycles is HSIZE and the total number of lines is the VSIZE.

These definitions of video frame periods are used for both Video Timing Detection and Video Timing Generation.

IMPORTANT: Note that pixels-per-clock for video data and timing is non-existent in the Video Timing Controller. There is only a single set of timing signals for the video data bus. This means that horizontal timing settings can be detected and generated only for a multiple of the pixels-per-clock configured in the system. For example, given a video format where the active line is 1920, the system configured with a video data bus operating at 4 pixels-per-clock, the detected and generated timing for the active line would be (1920 pixels / 4 pixels-per-clock) = 480 clocks. Similarly, all other horizontal components (i.e. hsync, hblank) would be effected, while the vertical components do not change.

The Video Timing Controller has six optional inputs for detecting the timing of the input video signal: vertical blank, vertical synchronization, horizontal blank, horizontal synchronization, active video and active chroma. The minimum set of inputs required to detect is either vertical blank, horizontal blank and active video or vertical sync, horizontal sync and active video. To enable detection, the Enable Detection GUI parameter must be set, and the control register bit 1 must also be set. The GUI parameter allows saving FPGA resources. The Control Register allows run-time flexibility. Other GUI parameters can be set to selectively disable detection of one or more input video timing signals.

The detected polarity of each input signal is shown by bits 0-5 of the Detection Polarity Register (address offset 0x2C). High denotes active high polarity, and low denotes active low polarity. Bits 8 and 9 of the Detection Encoding Register shows the number of lines skipped between each active chroma line. Bit 8 High denotes that every other line is skipped (4:2:0), and low denotes that no lines are skipped (4:4:4 or 4:2:2). Bit 9 High denotes that every other pixel is skipped, and low denotes that no pixels are skipped.

If any input (vblank_in, vsync_in, hblank_in, hsync_in, active_video_in, active_chroma_in) is not driven or is not connected, then detection for that input must be disabled. To disable detection for an input, deselect the appropriate option in the GUI ("Vertical Blank Detection", "Vertical Sync Detection", etc.).

The Video Timing Controller can generate up to six output video signals: vertical blank, vertical synchronization, horizontal blank, horizontal synchronization, active video and active chroma. To enable generation of these signals, the Enable Generation GUI parameter must be set, and the control register bit 0 or bit 2 must also be set. Other GUI parameters can be set to selectively disable generation of one or more video timing signals.

The polarity of each output signal can be set by bits 0-5 of the Generator Polarity Register (Address Offset 0x006C). High denotes active high polarity, and low denotes active low polarity. Bits 8 and 9 of the Control Register also sets the number of lines skipped between each active chroma line. Bit 8 High denotes that every other line is skipped (4:2:0), and low denotes that no lines are skipped (4:4:4 or 4:2:2). Bit 9 High denotes that every other pixel is skipped, and low denotes that no pixels are skipped.

The Video Timing Controller has bits in the Control Register called Source Selects to select the internal detection registers or the external input generation registers. These bits allow the detected timing (if enabled) to control the generated outputs or allow the host processor to override each value independently via the generation registers at address offset 0x0060 - 0x0084, as described in Table 2-7.

Table 3-1 through Table 3-6 show example settings of the input control busses and the resultant video timing output signals.

Programming the horizontal generation registers to the values shown in Table 3-1 will result in the video timing signal outputs shown in Figure 3-3.

Notice that in Table 3-1 the Control Register bit 2 is set to enable generation, that all source selects are set to 1 to select the Generation Registers and that the polarity bits are all set to 1 to configure the outputs for active high polarity.

Table 3‐1: Example Horizontal Generation Register Inputs

IMPORTANT: All signals are shown active high. The polarities of the output signals can be changed at any time via the GENERATOR POLARITY REGISTER (0x006C).

The following C code shows how to configure the register values in Table 3-1 using the Video Timing Controller driver.

 XVtc Vtc; /* Device driver instance */
XVtc_Signal SignalCfg; /* VTC Signal configuration */
XVtc_Polarity Polarity; /* Polarity configuration */
XVtc_SourceSelect SourceSelect;/* Source Selection configuration */

X-Ref Target - Figure 3-3

 XVtc_Config *VtcCfgPtr;
VtcCfgPtr = XVtc_LookupConfig(VTC_DEVICE_ID);
XVtc_CfgInitialize(&Vtc, VtcCfgPtr, VtcCfgPtr->BaseAddress);
/* Setup the VTC Source Select config structure. */
/* 1=Generator registers are source */
/* 0=Detector registers are source */
memset((void *)&SourceSelect, 0, sizeof(SourceSelect));
SourceSelect.VBlankPolSrc = 1;
SourceSelect.VSyncPolSrc = 1;
SourceSelect.HBlankPolSrc = 1;
SourceSelect.HSyncPolSrc = 1;
SourceSelect.ActiveVideoPolSrc = 1;
SourceSelect.ActiveChromaPolSrc= 1;
SourceSelect.VChromaSrc = 1;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 1;
SourceSelect.VSyncSrc = 1;
SourceSelect.VFrontPorchSrc = 1;
SourceSelect.VTotalSrc = 1;
SourceSelect.HActiveSrc = 1;
SourceSelect.HBackPorchSrc = 1;
SourceSelect.HSyncSrc = 1;
SourceSelect.HFrontPorchSrc = 1;
SourceSelect.HTotalSrc = 1;

/* Setup the VTC Polarity config structure. */
memset((void *)&Polarity, 0, sizeof(Polarity));
Polarity.ActiveChromaPol = 1;
Polarity.ActiveVideoPol = 1;
Polarity.VBlankPol = 1;
Polarity.VSyncPol = 1;
Polarity.HBlankPol = 1;
Polarity.HSyncPol = 1;

/* Setup the VTC Signal config structure. */
memset((void *)&SignalCfg, 0, sizeof(XVtc_Signal));
SignalCfg.OriginMode = 1;//Set Frame Origin to Start of Active Video
SignalCfg.HTotal = 7;
SignalCfg.HActiveStart = 0;
SignalCfg.HFrontPorchStart = 3;// Active Video Width
SignalCfg.HSyncStart = 4;// Active Video Width + FP Width
SignalCfg.HBackPorchStart = 5;// Active Video Width + FP Width + Sync Width

SignalCfg.V0Total = 7;
SignalCfg.V0ChromaStart = 0;
SignalCfg.V0ActiveStart = 0;
SignalCfg.V0FrontPorchStart = 3;// Active Video Height
SignalCfg.V0SyncStart = 4;// Active Video Height + FP_Width
SignalCfg.V0BackPorchStart = 5;// Active Video Height + FP Width + Sync Width
/* Write VTC config to HW */
XVtc_RegUpdate(&VTC);
XVtc_SetPolarity(&Vtc, &Polarity);
XVtc_SetGenerator(&Vtc, &SignalCfg);
XVtc_SetSource(&Vtc, &SourceSelect);

 /* Enable VTC Generator */
XVtc_Enable Generator(&Vtc);

Programming the generation registers to the values shown in Table 3-2 will result in the video timing signal outputs shown in Figure 3-4.

Notice that in Table 3-2 the Generator Encoding Register bits [3:0] are set to 0 to configure the number of lines skipped between each active chroma line to be 0. This configures the Active Chroma output signal for 4:4:4 or 4:2:2 mode in which every line contains valid chroma samples.

Table 3‐2: Example Vertical Generation Register Inputs

Figure 3‐4: Generated Vertical Timing (4:4:4 Chroma)

The following C code shows how to configure the register values in Table 3-2 using the Video Timing Controller driver.

 XVtc Vtc; /* Device driver instance */
XVtc_Signal SignalCfg; /* VTC Signal configuration */
XVtc_Polarity Polarity; /* Polarity configuration */
XVtc_SourceSelect SourceSelect;/* Source Selection configuration */
XVtc_Config *VtcCfgPtr;
VtcCfgPtr = XVtc_LookupConfig(VTC_DEVICE_ID);

X-Ref Target - Figure 3-4

 XVtc_CfgInitialize(&Vtc, VtcCfgPtr, VtcCfgPtr->BaseAddress);
/* Setup the VTC Source Select config structure. */
/* 1=Generator registers are source */
/* 0=Detector registers are source */
memset((void *)&SourceSelect, 0, sizeof(SourceSelect));
SourceSelect.VBlankPolSrc = 1;
SourceSelect.VSyncPolSrc = 1;
SourceSelect.HBlankPolSrc = 1;
SourceSelect.HSyncPolSrc = 1;
SourceSelect.ActiveVideoPolSrc = 1;
SourceSelect.ActiveChromaPolSrc= 1;
SourceSelect.VChromaSrc = 1;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 1;
SourceSelect.VSyncSrc = 1;
SourceSelect.VFrontPorchSrc = 1;
SourceSelect.VTotalSrc = 1;
SourceSelect.HActiveSrc = 1;
SourceSelect.HBackPorchSrc = 1;
SourceSelect.HSyncSrc = 1;
SourceSelect.HFrontPorchSrc = 1;
SourceSelect.HTotalSrc = 1;
/* Setup the VTC Polarity config structure. */
memset((void *)&Polarity, 0, sizeof(Polarity));
Polarity.ActiveChromaPol = 1;
Polarity.ActiveVideoPol = 1;
Polarity.VBlankPol = 1;
Polarity.VSyncPol = 1;
Polarity.HBlankPol = 1;
Polarity.HSyncPol = 1;
/* Setup the VTC Signal config structure. */
memset((void *)&SignalCfg, 0, sizeof(XVtc_Signal));
SignalCfg.OriginMode = 1;//Set Frame Origin to Start of Active Video
SignalCfg.HTotal = 7;
SignalCfg.HActiveStart = 0;
SignalCfg.HFrontPorchStart = 3;// Active Video Width
SignalCfg.HSyncStart = 4;// Active Video Width + FP Width
SignalCfg.HBackPorchStart = 5;// Active Video Width + FP Width + Sync Width
SignalCfg.V0Total = 8;
SignalCfg.V0ChromaStart = 0;
SignalCfg.V0ActiveStart = 0;
SignalCfg.V0FrontPorchStart = 4;// Active Video Height
SignalCfg.V0SyncStart = 5;// Active Video Height + FP_Width
SignalCfg.V0BackPorchStart = 6;// Active Video Height + FP Width + Sync Width
/* Write VTC config to HW */
XVtc_RegUpdate(&VTC);
XVtc_SetPolarity(&Vtc, &Polarity);
XVtc_SetGenerator(&Vtc, &SignalCfg);
XVtc_SetSource(&Vtc, &SourceSelect);
/* Enable VTC Generator */
XVtc_Enable Generator(&Vtc);

Programming the vertical generation registers to the values shown in Table 3-3 will result in the video timing signal outputs shown in Figure 3-5.

Notice that in Table 3-3 the Generator Encoding Register bits [3:0] are set to 0b0011 to configure the number of lines skipped between each active chroma line to be one line. This configures the Active Chroma output signal for 4:2:0 mode in which only every other line contains valid chroma samples.

Table 3‐3: Example Vertical Generation Register Inputs (4:2:0 Chroma)

The following C code shows how to configure the register values in Table 3-3 using the Video Timing Controller driver.

 XVtc Vtc; /* Device driver instance */
XVtc_Signal SignalCfg; /* VTC Signal configuration */
XVtc_Polarity Polarity; /* Polarity configuration */
XVtc_SourceSelect SourceSelect;/* Source Selection configuration */
XVtc_Config *VtcCfgPtr;
VtcCfgPtr = XVtc_LookupConfig(VTC_DEVICE_ID);
XVtc_CfgInitialize(&Vtc, VtcCfgPtr, VtcCfgPtr->BaseAddress);
/* Setup the VTC Source Select config structure. */

 /* 1=Generator registers are source */
/* 0=Detector registers are source */
memset((void *)&SourceSelect, 0, sizeof(SourceSelect));
SourceSelect.VBlankPolSrc = 1;
SourceSelect.VSyncPolSrc = 1;
SourceSelect.HBlankPolSrc = 1;
SourceSelect.HSyncPolSrc = 1;
SourceSelect.ActiveVideoPolSrc = 1;
SourceSelect.ActiveChromaPolSrc= 1;
SourceSelect.VChromaSrc = 1;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 1;
SourceSelect.VSyncSrc = 1;
SourceSelect.VFrontPorchSrc = 1;
SourceSelect.VTotalSrc = 1;
SourceSelect.HActiveSrc = 1;
SourceSelect.HBackPorchSrc = 1;
SourceSelect.HSyncSrc = 1;
SourceSelect.HFrontPorchSrc = 1;
SourceSelect.HTotalSrc = 1;
/* Setup the VTC Polarity config structure. */
memset((void *)&Polarity, 0, sizeof(Polarity));
Polarity.ActiveChromaPol = 1;
Polarity.ActiveVideoPol = 1;
Polarity.VBlankPol = 1;
Polarity.VSyncPol = 1;
Polarity.HBlankPol = 1;
Polarity.HSyncPol = 1;
/* Setup the VTC Signal config structure. */
memset((void *)&SignalCfg, 0, sizeof(XVtc_Signal));
SignalCfg.OriginMode = 1;//Set Frame Origin to Start of Active Video
SignalCfg.HTotal = 7;
SignalCfg.HActiveStart = 0;
SignalCfg.HFrontPorchStart = 3;// Active Video Width
SignalCfg.HSyncStart = 4;// Active Video Width + FP Width
SignalCfg.HBackPorchStart = 5;// Active Video Width + FP Width + Sync Width
SignalCfg.V0Total = 8;
SignalCfg.V0ChromaStart = 0;
SignalCfg.V0ActiveStart = 0;
SignalCfg.V0FrontPorchStart = 4;// Active Video Height
SignalCfg.V0SyncStart = 5;// Active Video Height + FP_Width
SignalCfg.V0BackPorchStart = 6;// Active Video Height + FP Width + Sync Width
/* Write VTC config to HW */
XVtc_RegUpdate(&VTC);
XVtc_SetPolarity(&Vtc, &Polarity);
XVtc_SetGenerator(&Vtc, &SignalCfg);
XVtc_SetSource(&Vtc, &SourceSelect);
XVtc_SetSkipLine(&Vtc, 1);
/* Enable VTC Generator */
XVtc_Enable Generator(&Vtc)

Programming the vertical generation registers to the values shown in Table 3-4 will result in the video timing signal outputs shown in Figure 3-6.

Notice that the Generator Encoding Register bits [3:0] are set to 0b0011, as in the previous example. Bits [9:8] of the Generator Encoding Register is set to 1 instead of 0. This configures the Active Chroma output signal for 4:2:0 mode, but with the opposite line set.

Table 3‐4: Example Vertical Generation Register Inputs (Alternate 4:2:0 Chroma)

Figure 3‐6: Generated Vertical Timing (Alternate 4:2:0 Chroma)

The following C code shows how to configure the register values in Table 3-4 using the Video Timing Controller driver.

 XVtc Vtc; /* Device driver instance */
XVtc_Signal SignalCfg; /* VTC Signal configuration */
XVtc_Polarity Polarity; /* Polarity configuration */
XVtc_SourceSelect SourceSelect;/* Source Selection configuration */
XVtc_Config *VtcCfgPtr;
VtcCfgPtr = XVtc_LookupConfig(VTC_DEVICE_ID);
XVtc_CfgInitialize(&Vtc, VtcCfgPtr, VtcCfgPtr->BaseAddress);
/* Setup the VTC Source Select config structure. */
/* 1=Generator registers are source */
/* 0=Detector registers are source */

 memset((void *)&SourceSelect, 0, sizeof(SourceSelect));
SourceSelect.VBlankPolSrc = 1;
SourceSelect.VSyncPolSrc = 1;
SourceSelect.HBlankPolSrc = 1;
SourceSelect.HSyncPolSrc = 1;
SourceSelect.ActiveVideoPolSrc = 1;
SourceSelect.ActiveChromaPolSrc= 1;
SourceSelect.VChromaSrc = 1;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 1;
SourceSelect.VSyncSrc = 1;
SourceSelect.VFrontPorchSrc = 1;
SourceSelect.VTotalSrc = 1;
SourceSelect.HActiveSrc = 1;
SourceSelect.HBackPorchSrc = 1;
SourceSelect.HSyncSrc = 1;
SourceSelect.HFrontPorchSrc = 1;
SourceSelect.HTotalSrc = 1;
/* Setup the VTC Polarity config structure. */
memset((void *)&Polarity, 0, sizeof(Polarity));
Polarity.ActiveChromaPol = 1;
Polarity.ActiveVideoPol = 1;
Polarity.VBlankPol = 1;
Polarity.VSyncPol = 1;
Polarity.HBlankPol = 1;
Polarity.HSyncPol = 1;
/* Setup the VTC Signal config structure. */
memset((void *)&SignalCfg, 0, sizeof(XVtc_Signal));
SignalCfg.OriginMode = 1;//Set Frame Origin to Start of Active Video
SignalCfg.HTotal = 7;
SignalCfg.HActiveStart = 0;
SignalCfg.HFrontPorchStart = 3;// Active Video Width
SignalCfg.HSyncStart = 4;// Active Video Width + FP Width
SignalCfg.HBackPorchStart = 5;// Active Video Width + FP Width + Sync Width
SignalCfg.V0Total = 8;
SignalCfg.V0ChromaStart = 0;
SignalCfg.V0ActiveStart = 1;
SignalCfg.V0FrontPorchStart = 4;// Active Video Height
SignalCfg.V0SyncStart = 5;// Active Video Height + FP_Width
SignalCfg.V0BackPorchStart = 6;// Active Video Height + FP Width + Sync Width
/* Write VTC config to HW */
XVtc_RegUpdate(&VTC);
XVtc_SetPolarity(&Vtc, &Polarity);
XVtc_SetGenerator(&Vtc, &SignalCfg);
XVtc_SetSource(&Vtc, &SourceSelect);
XVtc_SetSkipLine(&Vtc, 1);
/* Enable VTC Generator */
XVtc_Enable Generator(&Vtc);

Table 3-5 shows the detection register values for the source video timing in Figure 3-7. Programming the horizontal generation registers to the values shown in Table 3-6 will result in the video timing signal outputs shown in Figure 3-7.

Notice that all polarities bits are high in the Detection Polarity Register, signifying that all inputs are detected to have an active high polarity.

Notice, in the Control Register, that bit 2 is set to enable generation, bit 3 is set to enable detection and bit 5 is set to enable synchronizing the generated output to the detected inputs.

The Horizontal Size (ACTIVE_HSIZE_SRC) Source Select (bit 9 of the Control Register) is set to 1. All other source selects are low, signifying that all other detection registers should be used.

Also notice that the polarity of the output horizontal synchronization has been changed to active low by clearing bit 3 of the Generator Polarity Register.

IMPORTANT: All generated outputs remain synchronized to the inputs. The only changes made to the output are to the horizontal synchronization polarity and to the active video start and stop times.

The following C code shows how to configure the register values in Table 3-6 using the Video Timing Controller driver.

 XVtc Vtc; /* Device driver instance */
XVtc_Signal SignalCfg; /* VTC Signal configuration */
XVtc_Polarity Polarity; /* Polarity configuration */
XVtc_SourceSelect SourceSelect;/* Source Selection configuration */
XVtc_Config *VtcCfgPtr;
VtcCfgPtr = XVtc_LookupConfig(VTC_DEVICE_ID);
XVtc_CfgInitialize(&Vtc, VtcCfgPtr, VtcCfgPtr->BaseAddress);
/* Setup the VTC Source Select config structure. */
/* 1=Generator registers are source */
/* 0=Detector registers are source */
memset((void *)&SourceSelect, 0, sizeof(SourceSelect));
SourceSelect.VBlankPolSrc = 0;
SourceSelect.VSyncPolSrc = 0;
SourceSelect.HBlankPolSrc = 0;
SourceSelect.HSyncPolSrc = 1;
SourceSelect.ActiveVideoPolSrc = 0;
SourceSelect.ActiveChromaPolSrc= 0;
SourceSelect.VChromaSrc = 0;
SourceSelect.VActiveSrc = 1;
SourceSelect.VBackPorchSrc = 0;
SourceSelect.VSyncSrc = 0;
SourceSelect.VFrontPorchSrc = 0;
SourceSelect.VTotalSrc = 0;
SourceSelect.HActiveSrc = 0;
SourceSelect.HBackPorchSrc = 0;
SourceSelect.HSyncSrc = 0;
SourceSelect.HFrontPorchSrc = 0;
SourceSelect.HTotalSrc = 0;

 /* Setup the VTC Polarity config structure. */
memset((void *)&Polarity, 0, sizeof(Polarity));
Polarity.ActiveChromaPol = 1;
Polarity.ActiveVideoPol = 1;
Polarity.VBlankPol = 1;
Polarity.VSyncPol = 1;
Polarity.HBlankPol = 1;
Polarity.HSyncPol = 0;
/* Setup the VTC Signal config structure. */
memset((void *)&SignalCfg, 0, sizeof(XVtc_Signal));
SignalCfg.OriginMode = 1;//Set Frame Origin to Start of Active Video
SignalCfg.HTotal = 7;
SignalCfg.HActiveStart = 0;
SignalCfg.HFrontPorchStart = 1;// Active Video Width
SignalCfg.HSyncStart = 3;// Active Video Width + FP Width
SignalCfg.HBackPorchStart = 4;// Active Video Width + FP Width + Sync Width
SignalCfg.V0Total = 8;
SignalCfg.V0ChromaStart = 0;
SignalCfg.V0ActiveStart = 0;
SignalCfg.V0FrontPorchStart = 4;// Active Video Height
SignalCfg.V0SyncStart = 5;// Active Video Height + FP_Width
SignalCfg.V0BackPorchStart = 6;// Active Video Height + FP Width + Sync Width
/* Write VTC config to HW */
XVtc_RegUpdate(&VTC);
XVtc_SetPolarity(&Vtc, &Polarity);
XVtc_SetGenerator(&Vtc, &SignalCfg);
XVtc_SetSource(&Vtc, &SourceSelect);
XVtc_EnableSync&Vtc);// Synchronize the Generator to the Detector
/* Enable VTC Generator and Detector*/
XVtc_Enable(&Vtc);

Generation of the video timing output signals can be synchronized to the detected video timing input signals or generated independently by setting the SYNC_ENABLE field in the control register or selecting the GUI option to synchronize the generator to detector or fsync_in. Synchronization allows the generator to follow the phase of the detector timing. Synchronization of the output to the input allows the developer to override each individual timing signal with different settings such as signal polarity or start time. For example, the active video signal could be regenerated shifted one cycle earlier or later. This provides a flexible method for regenerating video timing output signals with different settings while remaining synchronized to the input timing.

The Video Timing Controller also has a GUI parameter, called Auto Generation Mode, to control the behavior of the generated outputs based on the detected inputs. When the Auto Generation Mode parameter is set, the generated video timing outputs will change based on the detected inputs. If this parameter is not set, then the video timing outputs will be generated based on only the first detected input format. (If the detector loses lock, the generated outputs will continue to be generated.) To change output timing while Auto

Generation Mode is set, timing detection must first be disabled by clearing bit 1 in the Control Register and then re-enabling, if any of the Source Select bits are low.

The Video Timing Controller has a frame synchronization output bus. Each bit can be configured to toggle high for any one clock cycle during each video frame. Each bit is independently configured for horizontal and vertical clock cycle position with the Frame Sync Configuration Registers (address offsets 0x0100 - 0x013c).

The Video Timing Controller has an active high interrupt output port named "irq". This output is set high when an interrupt occurs and set low when the interrupt event has been cleared. The Video Timing Controller also contains three 32-bit registers for configuring and reporting status of interrupts: the Interrupt Status/Clear, the Interrupt Enable and the Interrupt Clear Registers. A logical AND is performed on the Interrupt Enable Register and the Interrupt Status Register to set the interrupt output high. The Interrupt Clear Register is used to clear the Interrupt Status Register. Writing a '1' to a bit in the Interrupt Status Register clears the corresponding interrupt when set. Writing a '1' to a bit that is cleared, will have no effect.

This section illustrates likely usage scenarios for the Xilinx Video Timing Controller core.

Figure 3‐8: Example Video Timing Controller Use Model

Figure 3-8 shows four features of the Video Timing Controller being utilized in a video system:

• Detection of the source video frame timing
• Generation of video timing signals
• Generation of two Frame Syncs to control the Video Processors
• Connection to a Host Processor via the AXI4-Lite interface

To detect the timing of the source video, the timing signals are connected to the Video Timing Controller Detection Module. Both the timing and the signal polarity of the timing signals are captured and easily read by the host processor.

Video timing signals are generated to control a AXI4-Stream to Video-Out module and an external display. The timing of these output signals is controlled by the host processor. The Video Timing Controller can be configured in real-time to replicate the source video format or to slightly change the format on the output, for example, in cases where the input signals are positive polarity yet the display requires negative polarity synchronization signals. The Video Timing Controller can also be reconfigured in real-time to output a completely different format from the input source.

Two Frame Sync outputs are generated to control Video Processor 1 and Video Processor 2. These outputs could be used to control when Video Processor 2 starts processing relative to X-Ref Target - Figure 3-9

when Video Processor 1 starts processing. These Frame Syncs can be reconfigured in real-time as well.

The Video Timing Controller is connected to a Host Processor in this example. The AXI4-Lite Interface allows for easy connection between status/control registers and the host processor. In addition, the Video Timing Controller interrupt output can also be used to synchronize the software with hardware events.

If the video system requires that only complete video frames are sent from the Video-In To AXI4-Stream core, then the Video Timing Controller must be configured to drive the axis_enable input with bit 8 of the INTC_IF bus. This bus must be enabled with the "Include INTC Interface".

Figure 3‐9: Video Timing Controller Generator Synchronization Use Model

Figure 3-9 shows the ability of the Video Timing Controller to synchronize the timing generator to an incoming frame sync, vertical sync or vertical blank signal. This is useful to generate timing signals that are not present. For example, if blank signals can be generated from sync signals. Also, this allows the timing generator to synchronize to a separate timing generator

In this example, the bottom timing generator can be synchronized to the top timing controller, a separate vsync or separate vblank signal. This is controlled by the mux "Select" signal.

IMPORTANT: The timing generator can be offset from the input by configuring the Generator Global Delay Register (Address Offset 0x140)]

Once the fsync_in input is selected, the pixel or line offset delay of the synchronized generator can be configured with the Generator Global Delay Register.

The Video Timing Controller core has two clock sources, CLK and S_AXI_ACLK, one for each clock domain. The Video Timing Controller core also has four clock enable sources: CLK, DET_CLKEN, GEN_CLKEN and S_AXI_ACLKEN.

The input and output video timing interfaces use the CLK clock signal as their shared clock reference.

The AXI4-Lite interface uses the S_AXI_ACLK pin as its clock source. The CLK pin is not shared between the AXI4-Lite and video timing interfaces. The Video Timing Controller core contains clock-domain crossing logic between the CLK (video timing) and S_AXI_ACLK (AXI4-Lite) clock domains. The core automatically ensures that the AXI4-Lite transactions completes even if the video processing is stalled with RESETn, CLKEN or with the video clock not running.

The Video Timing Controller core has multiple enable options: the CLKEN pin (hardware clock enable), and the software enable option provided via the AXI4-Lite control interface (when present).

The CLKEN pin cannot ensure synchronization internally to video timing processing therefore de-asserting CLKEN for extended periods of time may lead to generating incomplete frames or lengthening the period needed to detect incoming video frame timing.

The CLKEN pin facilitates:

• Multi-cycle path designs (high speed clock division without clock gating),
• Standby operation of subsystems to save on power
• Hardware controlled bring-up of system components

The Video Timing Controller core also has a separate clock enable input pin to control the detector. This clock enable allows halting the detector independently from the generator.

The Video Timing Controller core also has a separate clock enable input pin to control the generator. This clock enable allows halting the generator independently from the detector.

The S_AXI_ACLKEN is the clock enable signal for the AXI4-Lite interface only. Driving this signal low only affects the AXI4-Lite interface and does not halt the video timing processing in the CLK clock domain.

The Video Timing Controller core has two reset pins, RESETn and S_AXI_ARESETn, one for each clock domain. Both resets are active low.

The Video Timing Controller core has two reset sources: the RESETn pin (hardware reset), and the software reset provided via the AXI4-Lite control interface (when present). The software reset is available via the control register at address offset 0x0000, bit 31.

IMPORTANT: RESETn is not synchronized internally to the video timing processing. De-asserting RESETn while frame timing is being process can lead to incomplete frames (from the generator).

The external reset pulse needs to be held for at least 32 CLK cycles to reset the core. The RESETn signal only resets the video timing interfaces and processing of the core. The AXI4-Lite interface is unaffected by the RESETn signal to allow the video timing processing core to be reset without halting the AXI4-Lite interface. However, if the RESETn is asserted low during an AXI4-Lite register read or write, the AXI4-Lite interface asserts the slave error response (0x2) for all addresses.

IMPORTANT: When a system with multiple-clocks and corresponding reset signals are being reset, the reset generator has to ensure all signals are asserted/de-asserted long enough so that all interfaces and clock-domains are correctly reinitialized.

The S_AXI_ARESETn signal is synchronous to the S_AXI_ACLK clock domain, but is internally synchronized to the CLK clock domain. The S_AXI_ARESETn signal resets the entire core including the AXI4-Lite and video timing interfaces.

The Video Timing Controller core register interface is compliant with the AXI4-Lite interface.

This chapter includes information about using Xilinx tools to customize and generate the core in the Vivado® Design Suite environment.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

• 1. Select the IP from the IP catalog.
• 2. Double-click on the selected IP or select the Customize IP command from the toolbar or popup menu.

For details, see the sections, "Working with IP" and "Customizing IP for the Design" in the Vivado Design Suite User Guide: Designing with IP (UG896) ](https://www.xilinx.com/support/documentation/sw_manuals_j/v=latest/ug910-vivado-getting-started.pdf|[#page-88-3|%5C[Ref) [Ref [5](#page-88-4).

If you are customizing and generating the core in the Vivado IP Integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994) [Ref [7](#page-88-5) for detailed information. IP Integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value you can run the validate_bd_design command in the Tcl console.

Note: Figures in this chapter are illustrations of the Vivado IDE. This layout might vary from the current version.

The Xilinx Video Timing Controller core is easily configured to meet the developer's specific needs through the Vivado tools graphical user interface (Figure 4-1, Figure 4-2). This section provides a quick reference to parameters that can be configured at generation time. X-Ref Target - Figure 4-1

Figure 4‐1: Vivado IP Catalog GUI - Main Window

X-Ref Target - Figure 4-2

Figure 4‐2: Vivado IP Catalog GUI - Default/Constant Mode Options Tab

Figure 4‐3: Vivado IP GUI - Frame Sync Position Tab

The GUI displays a representation of the IP symbol on the left side and the parameter assignments on the right side, described as follows:

• Component Name: The component name is used as the base name of output files generated for the module. Names must begin with a letter and must be composed from characters: a to z, 0 to 9 and "_". Note: The name v_tc_v6_1 is not allowed.

• Optional Features:

  • ° Include AXI4-Lite Interface: When selected, the core is generated with an AXI4-Lite interface, which gives access to dynamically program and change processing parameters. For more information, refer to Chapter 2, Core Interfaces.
  • ° Include INTC Interface: When selected, the core generates the optional INTC_IF port, which gives parallel access to signals indicating frame processing status and error conditions. For more information, refer to Interrupts in Chapter 2.
    • Interlaced Video Support: When selected, the core is generated with interlaced video detection and/or generation enabled.
    • Synchronize Generator to Detector or to fsync_in: When selected, the timing generator automatically synchronizes to the detector or to the fsync_in input port. Otherwise, the generator runs in free-run mode.

• Options:

  • ° Maximum Clocks per Line: This parameter sets the maximum number of clock cycles per video line that the Video Timing Controller can generate or detect. Values of 128, 256, 512, 1024, 2048, 4096 and 8192 are valid.
  • ° Maximum Lines per Frame: This parameter sets the maximum number of lines per video frame that the Video Timing Controller can generate or detect. Values of 128, 256, 512, 1024, 2048, 4096 and 8192 are valid.
  • ° Frame Syncs: This parameter sets the number of frame synchronization outputs to generate and supports up to 16 independent outputs.
  • ° Enable Generation: This parameter enables or disables the video timing outputs.
  • ° Enable Detection: This parameter enables or disables the detecting the timing of the video inputs.
  • ° Generation Options:
    • Field ID Generation: This parameter enables or disables generating the field ID output.
    • Vertical Blank Generation: This parameter enables or disables generating the vertical blank output.
    • Horizontal Blank Generation: This parameter enables or disables generating the horizontal blank output.
    • Vertical Sync Generation: This parameter enables or disables generating the vertical synchronization output.
    • Horizontal Sync Generation: This parameter enables or disables generating the horizontal synchronization output.
    • Active Video Generation: This parameter enables or disables generating the active video output.
    • Active Chroma Generation: This parameter enables or disables generating the active chroma output.
    • Auto Generation Mode: When enabled, this parameter will cause the generated video timing outputs to change based on the detected inputs. If this parameter is disabled, the video timing outputs will be generated based on only the first detected input format. The output for the generated synchronization signals will continue even if the detection block loses lock. This parameter is available only if both the Enable Generation and Enable Detection parameters are enabled. Note: This parameter has an effect only if one or more of the source select control register bits are set to low.
  • ° Detection Options:
    • Field ID Detection: This parameter enables or disables detecting the field id input.

• Vertical Blank Detection: This parameter enables or disables detecting the vertical blank input. If the vblank_in input will not be connected, then the Vertical Blank Detection option must be deselected.

• Horizontal Blank Detection: This parameter enables or disables detecting the horizontal blank input. If the hblank_in input will not be connected, then the Horizontal Blank Detection option must be deselected.

• Vertical Sync Detection: This parameter enables or disables detecting the vertical synchronization input. If the vsync_in input will not be connected, then the Vertical Sync Detection option must be deselected.

• Horizontal Sync Detection: This parameter enables or disables detecting the horizontal synchronization input. If the hsync_in input will not be connected, then the Horizontal Sync Detection option must be deselected.

• Active Video Detection: This parameter enables or disables detecting the active video input. If the active_video_in input will not be connected, then the Active Video Detection option must be deselected.

• Active Chroma Detection: This parameter enables or disables detecting the active chroma input. If the active_chroma_in input will not be connected, then the Active Chroma Detection option must be deselected.

• Constant/Default Timing Generation Options:

  • ° Video Format:
    • Video Mode: This parameter sets the default video format and controls the Horizontal, Vertical and Horizontal Fine Adjustment settings below. Values of 720p, 480p, 576p, 1080p, 352x288p, 352x576p, 480x576p, 544x575p, 704x576p, 704x480p, 640x480p, 800x600p, 1024x768p, 1280x1024p, 1600x1200p or Custom are valid. The interlaced video modes of 1080i, 480i and 576i are also available when the Interlaced Support parameter is checked. Video Modes are removed or added to this list based upon the sizes selected in the Max Clocks per Line and Max Lines per Frame parameters.
    • Chroma Format: This parameter sets the default value of the video format in the GENERATOR ENCODING register at address offset 0x68. This controls the behavior of the active_chroma_out output port.
    • Chroma Parity: This parameter sets the default value of the chroma parity in the GENERATOR ENCODING register at address offset 0x68. This controls the behavior of the active_chroma_out output port.
  • ° Horizontal Settings:
    • Active Size: This parameter sets the default number of clock cycles per frame (without blanking) in the GENERATOR ACTIVE_SIZE register at address offset 0x060.
    • Frame Size: This parameter sets the default number of clock cycles per frame (with blanking) in the GENERATOR HSIZE register at address offset 0x70.

• Sync Start: This parameter sets the default value of the clock cycle count during which the horizontal sync starts in the GENERATOR HSYNC register at address offset 0x78.

• Sync End: This parameter sets the default value of the clock cycle count during which the horizontal sync ends in the GENERATOR HSYNC register at address offset 0x78.

• ° Frame/Field 0 Vertical Settings:

  • Active Size: This parameter sets the default number of lines per frame (without blanking) in the GENERATOR ACTIVE_SIZE register at address offset 0x060.
  • Frame Size: This parameter sets the frame/field 0 default number of lines per frame size (with blanking) in the GENERATOR VSIZE register at address offset 0x74, bits 12:0.
  • Sync Start: This parameter sets the default value of the line count during which the vertical sync starts in the GENERATOR F0_VSYNC_V register at address offset 0x80.
  • Sync End: This parameter sets the default value of the line count during which the vertical sync ends in the GENERATOR F0_VSYNC_V register at address offset 0x80.

• ° Frame/Field 0 Horizontal Fine Adjustment:

  • Vblank Start: This parameter sets the default value of the clock cycle count during which the vertical blank starts in the GENERATOR F0_VBLANK_H register at address offset 0x7C.
  • Vblank End: This parameter sets the default value of the clock cycle count during which the vertical blank ends in the GENERATOR F0_VBLANK_H register at address offset 0x7C.
  • VSync Start: This parameter sets the default value of the clock cycle count during which the vertical sync starts in the GENERATOR F0_VSYNC_H register at address offset 0x84.
  • Vsync End: This parameter sets the default value of the clock cycle count during which the vertical sync ends in the GENERATOR F0_VSYNC_H register at address offset 0x84.

• ° Field 1 Vertical Settings:

  • Interlaced: This parameter enables generating interlaced video and sets the Interlaced bit (6) in the GENERATOR ENCODING register to 1. This parameter is only available when the Interlaced Video Support parameter is enabled.
  • Frame Size: This parameter sets the Field 1 default number of lines per frame size (with blanking) in the GENERATOR VSIZE register at address offset 0x74, bits 28:16.

• Sync Start: This parameter sets the Field 1 default value of the line count during which the vertical sync starts in the GENERATOR F1_VSYNC_V register at address offset 0x8C.

• Sync End: This parameter sets the Field 1 default value of the line count during which the vertical sync ends in the GENERATOR F1_VSYNC_V register at address offset 0x8C.

• Vblank Start: This parameter sets the Field 1 default value of the clock cycle count during which the vertical blank starts in the GENERATOR F1_VBLANK_H register at address offset 0x88.
• Vblank End: This parameter sets the Field 1 default value of the clock cycle count during which the vertical blank ends in the GENERATOR F1_VBLANK_H register at address offset 0x88.
• VSync Start: This parameter sets the Field 1 default value of the clock cycle count during which the vertical sync starts in the GENERATOR F1_VSYNC_H register at address offset 0x90.
• Vsync End: This parameter sets the Field 1 default value of the clock cycle count during which the vertical sync ends in the GENERATOR F1_VSYNC_H register at address offset 0x90.
• ° Active Polarity:
  • Field ID: This parameter sets the polarity of the field_id_out signal. Values of Active High or Active Low are valid. This parameter is enabled when the Interlaced Video Support and Interlaced parameters are enabled.
  • Vblank: This parameter sets the polarity of the vblank_out signal. Values of Active High or Active Low are valid.
  • Hblank: This parameter sets the polarity of the hblank_out signal. Values of Active High or Active Low are valid.
  • Vsync: This parameter sets the polarity of the vsync_out signal. Values of Active High or Active Low are valid.
  • Hsync: This parameter sets the polarity of the hsync_out signal. Values of Active High or Active Low are valid.
  • Active Video: This parameter sets the polarity of the active_video_out signal. Values of Active High or Active Low are valid.
  • Active Chroma: This parameter sets the polarity of the active_chroma_out signal. Values of Active High or Active Low are valid.
• ° Frame Sync Position:
• Frame Sync # Horizontal Position: These parameters set the default value of the clock cycle count during which Frame Sync # is active in the FRAME SYNC 0-15 CONFIG registers at address offset 0x100-0x13c.
• Frame Sync # Vertical Position: These parameters set the default value of the line count during which Frame Sync # is active in the FRAME SYNC 0-15 CONFIG registers at address offset 0x100-0x13c.

Note: The parameter values within the Constant/Default Timing Generation Options will also be the values used during timing generation when the Include AXI4-Lite Register Interface parameter is disabled. These parameter values will be used when the core is in constant mode when it does not have an AXI4-Lite interface.

Vivado generates the files necessary to build the core and place those files in the /.srcs/sources_1/ip/ directory.

The Vivado tools output consists of some or all the following files.

Table 4‐1: Vivado Software Output

The only constraints required are clock frequency constraints for the video clock, clk, and the AXI4-Lite clock, s_axi_aclk. Paths between the two clock domains should be constrained with a max_delay constraint and use the datapathonly flag, causing setup and hold checks to be ignored for signals that cross clock domains. These constraints are provided in the XDC constraints file included with the core.

This chapter contains information about simulating IP in the Vivado® Design Suite environment. For comprehensive information about Vivado simulation components, as well as information about using supported third party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref [6](#page-88-6)

For details about synthesis and implementation, see "Synthesizing IP" and "Implementing IP" in the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref [3](#page-88-3)

No example design is available at the time for the Video Timing Controller v6.1 core.

This chapter contains information about the provided test bench in the Vivado® Design Suite environment.

A demonstration test bench is provided with the core which enables you to observe core behavior in a typical scenario. This test bench is generated together with the core in Vivado Design Suite. You are encouraged to make simple modifications to the configurations and observe the changes in the waveform.

The following files are expected to be generated in the in the demonstration test bench output directory:

• axi4lite_mst.v
• axi4s_video_mst.v
• axi4s_video_slv.v
• ce_generator.v
• tb_<IP_instance_name>.v

The top-level entity is tb_<IP_instance_name>.

It instantiates the following modules:

• DUT The core instance under test.

• axi4lite_mst The AXI4-Lite master module, which initiates AXI4-Lite transactions to program core registers.

• axi4s_video_mst The AXI4-Stream master module, which generates ramp data and initiates AXI4-Stream transactions to provide video stimuli for the core and can also be used to open stimuli files and convert them into corresponding AXI4-Stream transactions.

To do this, edit tb_<IP_instance_name>.v:

• a. Add define macro for the stimuli file name and directory path define STIMULI_FILE_NAME.
• b. Comment-out/remove the following line: MST.is_ramp_gen(C_ACTIVE_ROWS, C_ACTIVE_COLS, 2); and replace with the following line: MST.use_file(`STIMULI_FILE_NAME);
• axi4s_video_slv

The AXI4-Stream slave module, which acts as a passive slave to provide handshake signals for the AXI4-Stream transactions from the core output, can be used to open the data files and verify the output from the core.

To do this, edit tb_<IP_instance_name>.v:

• a. Add define macro for the golden file name and directory path define GOLDEN_FILE_NAME "".
• b. Comment out the following line: SLV.is_passive; and replace with the following line: SLV.use_file(`GOLDEN_FILE_NAME);
• ce_gen

Programmable Clock Enable (ACLKEN) generator.

A highly parameterizable test bench was used to test the Video Timing Controller core. Testing included the following:

• Register accesses
• Processing of multiple frames of data
• Testing of various frame sizes including 1080p, 720p, and 480p
• Varying instantiations of the core
• Varying the polarity of input and output signals
• Varying the horizontal offset of the vertical timing signals
• Regenerating the input on the output
• Testing of various interrupts

The Video Timing Controller core has been tested in a variety of hardware platforms at Xilinx to represent a variety of parameterizations, including the following:

• A test design was developed for the core that incorporated a MicroBlaze™ processor, AXI4 Interconnect and various other peripherals. The software for the test system included live video input for the Video Timing Controller core. The Video Timing Controller, in addition to live video, was also connected in loopback allow the generator to feed the detector for a robust loopback test. Various tests could be supported by varying the configuration of the Timing Controller core or by loading a different software executable. The MicroBlaze processor was responsible for:
  • ° Initializing the appropriate input and output buffers in external memory.
• ° Initializing the Video Timing Controller core.
• ° Initializing the HDMI/DVI input and output cores for live video.
• ° Launching the test.
• ° Configuring the Video Timing Controller for various input frame sizes and checking the detection/generation loopback connection for correct video detection
• ° Controlling the peripherals including the UART and AXI VDMAs.

This appendix contains information about migrating from an ISE design to the Vivado Design Suite, and for upgrading to a more recent version of the IP core. For customers upgrading their IP core, important details (where applicable) about any port changes and other impact to user logic are included.

For information about migration to Vivado Design Suite, see ISE to Vivado Design Suite Migration Guide (UG911) [Ref [2](#page-88-7).

This section provides information about any changes to the user logic or port designations that take place when you upgrade to a more current version of this IP core in the Vivado Design Suite.

The Video Timing Controller v5.00.a added parameters for configuring the core in constant mode, thus the core can be initialized to generate timing after reset without a processor or software.

The Video Timing Controller v5.00.a removed all GPP interface ports. The Video Timing Controller v4.00.a.0 added the ability to operate on video frame sizes up to 8192 x 8192. Previous versions supported 4096 x 4096 maximum. If the maximum sizes of 8192 are selected, some GPP ports will be 13 bits wide where on previous versions of the core, these ports were 12 bits.

The Video Timing Controller v4.00.a also added the ability to detect and generate vertical signals with a horizontal offset. In order to report the horizontal start cycle of these vertical signals, the Video Timing Controller v4.00.a added the following new ports:

• gen_v0blank_hstart
• gen_v0blank_hend
• gen_v0sync_hstart
• gen_v0sync_hend
• det_v0blank_hstart
• det_v0blank_hend
• det_v0sync_hstart
• det_v0sync_hend

The Video Timing Controller v4.00.a changed from the PLB processor interface to the AXI4-Lite interface. As a result, all of the PLB-related connections have been replaced with an AXI4-Lite interface. For more information, see the AXI Reference Guide [Ref [1](#page-88-2).

The Video Timing Controller v5.00.a AXI4-Lite register definitions changed from the previous version, simplifying the address map. The Video Timing Controller v5.00.a also added parameters for configuring the core in constant mode, thus the core can be initialized to generate timing after reset without a processor or software. The Video Timing Controller v3.0 added the ability to operate on video frame sizes up to 8192 x 8192. Previous versions supported 4096 x 4096 maximum.

The Video Timing Controller v3.0 also added the ability to detect and generate vertical signals with a horizontal delay offset.

The Video Timing Controller v3.0 added the support for the AXI4-Lite interface with this version. When using the Video Timing Controller v3.0, note that the core name changed from "timebase" to "axi_vtc". All software driver functions, data structures and filenames also changed from a "xtimebase" prefix to "xvtc" prefix.

Appendix C

This appendix includes details about resources available on the Xilinx Support website and debugging tools.

To help in the design and debug process when using the Video Timing Controller, the Xilinx Support web page contains key resources such as product documentation, release notes, answer records, information about known issues, and links for opening a Technical Support Web Case.

This product guide is the main document associated with the Video Timing Controller. This guide, along with documentation related to all products that aid in the design process, can be found on the Xilinx Support web page or by using the Xilinx Documentation Navigator.

Download the Xilinx Documentation Navigator from the Downloads page. For more information about this tool and the features available, open the online help after installation.

Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a Xilinx product. Answer Records are created and maintained daily ensuring that users have access to the most accurate information available.

Answer Records for this core are listed below, and can also be located by using the Search Support box on the main Xilinx support web page. To maximize your search results, use proper keywords such as

• Product name
• Tool message(s)
• Summary of the issue encountered

A filter search is available after results are returned to further target the results.

AR 54541 http://Xilinx Support web page/answers/54541.htm

Xilinx provides technical support in the Xilinx Support web page for this LogiCORE™ IP product when used as described in the product documentation. Xilinx cannot guarantee timing, functionality, or support if you do any of the following:

• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.

Xilinx provides premier technical support for customers encountering issues that require additional assistance.

To contact Xilinx Technical Support, navigate to the Xilinx Support web page.

• 1. Open a WebCase by selecting the WebCase link located under Support Quick Links.
• A block diagram of the video system that explains the video source, destination and IP (custom and Xilinx) used.

Note: Access to WebCase is not available in all cases. Please login to the WebCase tool to see your specific support options.

There are many tools available to address Video Timing Controller design issues. It is important to know which tools are useful for debugging various situations.

The Video Timing Controller is delivered with an example test bench. Information about the example test bench can be found in Chapter 6, Example Design for the Vivado Design Suite.

Vivado inserts logic analyzer and virtual I/O cores directly into your design. Vivado Lab Tools allows you to set trigger conditions to capture application and integrated block port signals in hardware. Captured signals can then be analyzed. This feature represents the

functionality in the Vivado IDE that is used for logic debugging and validation of a design running in Xilinx FPGA devices in hardware.

The Vivado logic analyzer is used to interact with the logic debug LogiCORE IP cores, including:

• ILA 2.0 (and later versions)
• VIO 2.0 (and later versions)

Various Xilinx development boards support Video Timing Controller. These boards can be used to prototype designs and establish that the core can communicate with the system.

• 7 series evaluation boards
  • ° KC705
  • ° ZC702

If the IP requires a license key, the key must be verified. The Vivado tool flows have a number of license check points for gating licensed IP through the flow. If the license check succeeds, the IP may continue generation. Otherwise, generation halts with error. License checkpoints are enforced by the following tools:

• RDS
• RDI
• Bitgen

IMPORTANT: IP license level is ignored at checkpoints. The test confirms a valid license exists. It does not check IP license level.

Hardware issues can range from link bring-up to problems seen after hours of testing. This section provides debug steps for common issues. The ChipScope tool is a valuable resource to use in hardware debug. The signal names mentioned in the following individual sections can be probed using the ChipScope tool for debugging the specific problems.

Many of these common issues can also be applied to debugging design simulations. Details are provided on General Checks

Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation.

• Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this could indicate a PCB issue. Ensure that all clock sources are active and clean.
• If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the LOCKED port.
• If your outputs go to 0, check your licensing. The evaluation version of the core will time out after running for 8 hours at 75 MHz.

The Video Timing Controller hardware evaluation core times out after approximately eight hours of operation. The output is driven to zero. This results in a dark-green screen for YUV color systems and possibly loss of lock on output monitors.

Table C-1 describes how to troubleshoot the AXI4-Lite interface.

Assuming the AXI4-Lite interface works, the second step is to bring up the AXI4-Stream interfaces.

Table C-2 describes how to troubleshoot third-party interfaces.

Table C‐2: Troubleshooting Third-Party Interfaces

For support resources such as Answers, Documentation, Downloads, and Forums, see the Xilinx Support website at:

http://Xilinx Support web page.

For a glossary of technical terms used in Xilinx documentation, see:

https://www.xilinx.com/support/documentation/sw_manuals/glossary.pdf.

For a comprehensive listing of Video and Imaging application notes, white papers, reference designs and related IP cores, see the Video and Imaging Resources page at:

[](https://www.xilinx.com/esp/video/refdes_listing.htm#ref_des.](https://www.xilinx.com/esp/video/refdes_listing.htm#ref_des.](https://www.xilinx.com/esp/video/refdes_listing.htm#ref_des)

Xilinx Documentation Navigator provides access to Xilinx documents, videos, and support resources, which you can filter and search to find information. To open the Xilinx Documentation Navigator (DocNav):

• From the Vivado IDE, select Help > Documentation and Tutorials.
• On Windows, select Start > All Programs > Xilinx Design Tools > DocNav.
• At the Linux command prompt, enter docnav.

Xilinx Design Hubs provide links to documentation organized by design tasks and other topics, which you can use to learn key concepts and address frequently asked questions. To access the Design Hubs:

• In the Xilinx Documentation Navigator, click the Design Hubs View tab.
• On the Xilinx website, see the Design Hubs page.

Note: For more information on Documentation Navigator, see the Documentation Navigator page on the Xilinx website.

These documents provide supplemental material useful with this user guide:

• 1. Vivado AXI Reference Guide (UG1037)
• 2. ISE to Vivado Design Suite Migration Guide (UG911)
• 3. Vivado Design Suite User Guide: Designing with IP (UG896)
• 4. Vivado Design Suite User Guide: Programming and Debugging (UG908)
• 5. Vivado Design Suite User Guide: Getting Started (UG910)
• 6. Vivado Design Suite User Guide: Logic Simulation (UG900)
• 7. Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994)

The following table shows the revision history for this document.

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