Kasli - cnourshargh/Bham-ARTIQ-examples GitHub Wiki

For official Kasli page, click here

Overview

Kasli is an FPGA (field programmable gate array) carrier. This is the board from which the rest of the Sinara device is controlled. It acts either as an ARTIQ master, or as a slave. As a master, the code is run on the FPGA and the Kasli board controlls all the other boards in its device and any connected devices. As a slave, it is controlled by a separate master via a DRTIO connector. We have not attempted using more than one Sinara device so have no experience using a Kasli in slave mode.

Specifications

Kasli contains an internal 125MHz clock. It has an SMA input to recieve and external clock if desired, however this requires a change to the gateware. Kasli also has a USB connection for JTAG testing of the device, checking diagnostics, and flashing the FPGA.Each Kasli Board can support upto 12 EEMs. It also has 3 user controlled LEDs.

Code Examples

LED_OnOffPulse.py

Code demonstrating basic use of an LED on the Kasli Board

• Switch LED on
• Switch LED off
• Pulse LED

LED_Parallel.py

Code demonstrating "with parallel" and "with sequential" statements by pulsing LEDs on Kasli Board

• Two parallel threads
• One of the parallel threads has sequential code within it

Schematic

For Kasli Schematic, click here.

Content To be Looked into

• External Clocking
  • I think this required a change to gateware that we were not able to implement as we did not have access to a Xilinx compiler
• UART/JTAG
  • The micro usb port on the front of the Kasli controller can be used for monitoring diagnostics and flashing the FPGA however we have not had time to look into this
• DRTIO between Sinara Devices
  • As we only have one Sinara device we have been unable to look into this feature at all