FPGA CNN Accelerator

accelerate neural net on FPGA

We implemented a basic hand-writing recognition neural net with C that includes basic matrix operations such as add and multiply. We got the model to run on the embedded ARM core on the FPGA while implemented the operations with SystemVerilog. Then we experimented the interface between the CPU and the FPGA and tried to replace the matrix operations with hardware implementation to speed up the calculations. Eventually everything works on simulation, but due to the limiting logic and memory capacity of our FPGA, we weren't able to fully synthesize everything.

Team Members

Team Member	Photo
Ying Meng
Felicia Liu
Andrew Liao
Mark Chen
Jessie Wang

Photos

https://drive.google.com/drive/folders/1CDeDJ-kiV5Ss8nBLyIUc2K2QiGjdkQVq?usp=sharing

Parts

Part	Unit Price	Quantity	Cost		Needs to be Ordered through Build18? (Y/N)	Part Link
DE10-Standard Development Kit (Academic)	365	1	365		N	https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1081&PartNo=7#contents
			36.8			shipping fee
		Total Cost:	401.8
		Remaining Budget:(out of $300)	-101.8