Super FX Registers - brunovalads/yoshisisland-disassembly GitHub Wiki
ALL REGISTERS ARE 16 BITS IN SIZE UNLESS OTHERWISE SPECIFIED
ALL REGISTERS HAVE R/W ACCESS FROM SCPU UNLESS OTHERWISE SPECIFIED
General Registers
$3000 -> r0 ; Default source/destination register
$3002 -> r1 ; PLOT instruction, X coordinate (init value $0000)
$3004 -> r2 ; PLOT instruction, Y coordinate (init value $0000)
$3006 -> r3 ;
$3008 -> r4 ; LMULT instruction, lower 16 bits
$300A -> r5 ;
$300C -> r6 ; FMULT and LMULT instructions, multiplication
$300E -> r7 ; MERGE instruction, source 1
$3010 -> r8 ; MERGE instruction, source 2
$3012 -> r9 ;
$3014 -> r10 ;
$3016 -> r11 ; LINK instruction destination register
$3018 -> r12 ; LOOP instruction counter
$301A -> r13 ; LOOP instruction branch
$301C -> r14 ; ROM address pointer for data loading
$301E -> r15 ; GSU program counter
$3030 -> SFR ; Status/Flag Register
format: $3031: status portion
IRQ | * | * | B | IH | IL | ALT2 | ALT1
$3030: flag portion
* | R | G | OV | S | CY | Z | *
key: IRQ: Interrupt flag
B: Set to 1 when the WITH instruction is executed
IH: Immediate higher 8-bit flag
IL: Immediate lower 8-bit flag
ALT2: Mode set-up flag for the next instruction
ALT1: Mode set-up flag for the next instruction
R: Set to 1 when reading ROM using r14 address
G: Go flag (set to 1 when the GSU is running)
OV: Overflow flag
S: Sign flag
CY: Carry flag
Z: Zero flag
*: Unused
Memory Operation Registers
$3034 -> PBR ; Program Bank Register (8 bits)
$3036 -> ROMBR ; ROM Bank Register (SCPU read-only) (8 bits)
$303C -> RAMBR ; RAM Bank Register (SCPU read-only) (8 bits)
format:
0 = bank $70
1 = bank $71
$303E -> CBR ; Cache Base Register (SCPU read-only)
(specifies starting address when loading data from ROM/RAM to cache RAM)
PLOT Registers
$3038 -> SCBR ; Screen Base Register (SCPU write-only) (8 bits)
(specifies starting address in the character data storage area)
(to calculate the starting address, use the following formula:
starting address = $700000 + (SCBR * $0400))
$303A -> SCMR ; Screen Mode Register (8 bits)
format: * | * | HT1 | RON | RAN | HT0 | MD1 | MD0
key:
Screen Height:
HT1 | HT0 | Mode
0 | 0 | 128 (pixels)
0 | 1 | 160 (pixels)
1 | 0 | 192 (pixels)
1 | 1 | OBJ mode
Color Gradient:
MD1 | MD0 | Mode
0 | 0 | 4-color mode
0 | 1 | 16-color mode
1 | 0 | unused
1 | 1 | 256-color mode
ROM/RAM Enable Flags:
RON: 0 = SCPU has ROM bus access
1 = GSU has ROM bus access
RAN: 0 = SCPU has RAM bus access
1 = GSU has RAM bus access
$xxxx -> COLR ; Color Register (no access from SCPU) (8 bits)
(specifies the colors to be plotted when the PLOT instruction is executed)
$xxxx -> POR ; Plot Option Register (no access from SCPU) (8 bits)
(specifies the mode to be used when a COLOR, GETC, or PLOT instruction is executed)
format:
* | * | * | OBJ Flag | Freeze High Flag | High Nybble Flag | Diter Flag | Transparent Flag
key: Flag Name | Operation when 0 | Operation when 1
Transparent Flag | Do not PLOT color 0 | PLOT color 0
Dither Flag | PLOT value of low 4 | Alternately PLOT high 4 bits and
| bits of color register | low 4 bits of color register
High Nybble Flag | Set value of low 4 | Set value of high 4
| bits in color register | bits in color register
Freeze High Nybble | Set all 8 bits in | Set only low 4 bits in color
Flag | color register | register with high 4 bits fixed
OBJ Mode Flag | Set mode with SCMR | OBJ mode
| (HT0,HT1) |
Other Registers
$3033 -> BRAMR ; Back-Up RAM Register (SCPU write-only) (8 bits)
format: 0 = BRAM is disabled
1 = BRAM is enabled
$303B -> VCR ; Version Code Register (SCPU read-only) (8 bits)
(permits the user to read the GSU version code)
$3037 -> CFGR ; Config Register (SCPU write-only) (8 bits)
(selects the operating speed of the multiplier in the GSU and sets up a mask for the interrupt signal)
format: IRQ | * | MS0 | * | * | * | * | *
key: IRQ: IRQ mask flag, set to 1 when the GSU interrupt request is masked
MS0: Multiplier Speed Selection
0 = Standard Speed Mode
1 = High Speed Mode
$3039 -> CLSR ; Clock Select Register (SCPU write-only) (8 bits)
(assigns GSU operating frequency)
format: 0 = GSU operates at 10.7 MHz
1 = GSU operates at 21.4 MHz
Other Notes
$3100~$32FF is where GSU cache RAM is located. It can be freely read to and written from by the SCPU as long as the GSU is not executing.
The benefit of doing this is having the GSU execute exclusively in cache RAM.
NOTE: The CBR isn't an SCPU address necessarily; the address complies with the low 9 bits of the CBR.
To calculate the CBR address for SCPU access use the following formula:
SCPU CBR address = $3100 + (CBR & $01FF)
NOTE: Writing to cache RAM from SCPU must be done in 16-byte blocks.
If data is written only partially in the blocks, the GSU will skip over that block entirely because the cache flag for that block wasn't set.
To set the cache flag for a given block, write any data to the $XXXF address of that block.