• Breakout:

  The combination of fanouts and escape traces, which allow routing out of the BGA pad array to the perimeter of the device prior to general routing of the PCB.

• Fanout Pattern:

  When adding fanouts to the BGA, enabling routing on the inner layer, the pattern may vary considerably depending on the layer stackup, via model, and pin density. The pattern may range from simple quadrant-matrix to a set of complex alternating arrangements. Using the appropriate fanout patttern will make a significant difference on the success of breakouk and routing of the BGA.

• Escape Route:

  A series of traces from fanout (via) to the perimeter of the package (courtyard).

• Perimeter:

  Outline of the package. Sometimes the perimeter extends a short distance to stay clear of vias which are part of the breakout.

• Via:

  A plated hole connecting different layers of a Printed Circuit Board, or PCB.

• Through Via:

  A via that extends from the top to the bottom of the board.

• Tented Via:

  A tented via is covered and sealed with a layer of solder mask, creating a protective, tent-like enclosure over the opening. This process provides several benefits, including preventing solder from wicking into the via, offering protection from environmental factors like dust and corrosion, preventing short circuits caused by stray solder, and helping to isolate electrical nets. However, it can hinder repair and probing, impede heat transfer, and risk trapping gases or etchants within the via, which can lead to long-term reliability issues.

• Blind Via:

  A via that begins on an outer layer and ends on an inner layer.

• Buried Via:

  This type of via starts and ends on an inner layer.

• Micro Via:

  This via has a hole diameter less than or equal to 0.15 mm. Often these are stacked on top of each other.

• Any Layer Via:

  These are short micro-vias that individually span only a pair of layers and are stacked together to result in a span between any two layers.

• NSEW Breakout:

  North, South, East, and West routing of the escape traces. This means the escape traces are routed in all four directions on the same layer.

• Layer Based Breakout:

  The escape traces are routed in the direction of the layer bias as oppossed to NSEW routing. Escape traces are also routed in the direction of the connection according to the layer bias.

• Layer Stackup:

  Early in the design process, the layer stackup will be defined. If the board has large and dense BGAs, High Density Interconnect (HDI) with a laminated core and buildup layers may be required. There are many different options using various materials and processes. Cost and reliability are usually the primary factors in determining the stackup and you will have to balance the tradeoff between layer count and fabrication processes to reach your goals.

• Via Models:

  Within the context of any given layer stackup, you have many options regarding via models. The decision on which type of via to use (through, laminated blind and buried or HDI micro vias) will likely be driven by the density of the board and the BGA packages. There are also options regarding vias inside pads and stacking that affect cost. In addition to this, board fabricators tend to focus on a limited set of processes thereby limiting your choice of vendors, depending on the technology you desire. From the design point of view, choosing the appropriate via models directly impacts the route-ability of the board.

• Design Rules:

  PCB fabricators continue to find methods that allow for further miniaturization and increased reliability. The design rules have to balance the tradeoffs between cost, signal integrity, and route-ability.

• Signal Integrity:

  Although the fabricators continue to improve their processes and produce reliable boards with smaller and features and clearances, maintaining signal integrity at high performance levels usually requires greater spacing between critical nets, especially to manage crosstalk effects at higher speeds. This conflict is exasperated with high pin-count and dense BGAs. Choosing appropriate layer stackups and via models will not only improve route-ability but signal integrity as well.

• Power Integrity: Managing power distribution effectively for large pin-count BGAs is a challenge and is significantly impacted by the layer stackup. There are methods that can minimize the number decoupling capacitors required, thereby increasing the space available for signal routing.

• Refdes:

  Short for "Reference designator". The refdes for a BGA package typically starts with the capital "U", followed by a sequence number.

Invoke the fanout tool with:

:Fanout(U1)

Update the ratlines by pressing the O key.

Below follows a rough outline of what the execution of events could look like:

• Check whether an argument was passed. If not, terminate the function.

• Check whether a single refdes was passed. If more than 1 refdes is passed, terminate the function.

• Create a fanout struct to store information in.

• Get the refdes of the argument.

• Find the element in the PCB layout struct.

• Determine the number of horizontal routes in a channel:

  $$number\ of\ horizontal\ routes=\frac{vertical\ pitch - pad\ diameter}{trace\ width + trace\ clearance}$$

• Determine the number of vertical routes in a channel:

  $$number\ of\ vertical\ routes=\frac{horizontal\ pitch - pad\ diameter}{trace\ width + trace\ clearance}$$