Mega UltraScale Notes - barawn/verilog-library-barawn GitHub Wiki

UG574's CARRY8 schematic is wrong

UG574 clearly shows that both the DI0 and CIN inputs can be driven from AX.

This is wrong: https://support.xilinx.com/s/article/63963

You cannot connect both DI0 and CIN to AX due to a restriction that's mentioned like, nowhere.

LVDS pins have absurd tri-state timing

The timing requirement on the tri-state features of UltraScale devices is absurdly larger than previous generations - it's approximately 1000 ns.