Mega Transceiver Notes - barawn/verilog-library-barawn GitHub Wiki

Gigabit Transceivers

"Full/Quarter/Half/Octal/Hex" rate

Xilinx throws these terms around in places (mainly eye scan) but never actually defines them. They're the ratio of the PLL clock to the data rate - equivalent to the RXOUT_DIV pins or RXRATE attributes. Divide by 1 = full rate, divide by 2 = half rate, etc. In the eye scan, you're slewing the PLL when you move the horizontal offset, so if you want to move a full unit interval (UI) you need to know how many PLL clocks correspond to a UI.

Manual eyescans

https://adaptivesupport.amd.com/s/article/67295?language=en_US

Note that the section on ES_SDATA_MASK in that article is just wrong: see p.224 in UG576, except be careful since their "Verilog bit lists" are wrong in that document: when they say 80'b1 they mean {80{1'b1}}. The example they're giving is for 40-bit data on an UltraScale device. For 40-bit data (32-bit output words/8b10b encoding) on an UltraScale+ device, it would be {80{1'b1}}, {40{1'b0}}, {40{1'b1}}. It's a data mask, if you have 32 bit data you should only have 32 zeros in the entire ES_SDATA_MASK word.

Data Width: not necessarily your data width!

The "Data Width" value in that document is the internal data width. Not the one that the user sees. See below for extracting the internal data width!

The TL;DR procedure for US+ Aurora

RMW means read-modify-write: read the DRP register, modify the bits you want, then write it back.

  1. Read 0x63 and extract bits [2:0]. Calculate 2^(this value) - that is the data rate. e.g. if bits [2:0] are 2, this is quad rate (RATE = 2^2 = 4).
  2. Read 0x03 and extract bits [3:0] to get the external bit width. The mapping goes 2=>16, 3=>20, 4=>32, 5=>40, 6=>64, 7=>80, 8=>128, 9=>160.
  3. Read 0x66 and extract bits [1:0] to get the divider. Divide the external bit width by 2^(divider). So if divider = 1, external width = 64, internal width is 32.
  4. Write 0x300 | ES_PRESCALE to 0x3C (Eyescan control reg). ES_PRESCALE goes from 0->31 (or 0 to 1F) and corresponds to PRESCALE = 2^(ES_PRESCALE+1) samples.
  5. GT RX reset (for Aurora this should just be GT reset)
  6. Write the mask values: these are in 0x49, 0x4A, 0x4B, 0x4C, 0x4D (first sample, low bits) and 0xF1, 0xF2, 0xF3, 0xF4, 0xF5 (second sample, high bits). For most cases you want to set the N highest bits of the first sample to zero, where N is the bit width from step 2. For instance, for 20 bits (0x03 bits [3:0] = 3), you write 0xFF to 0x49, 0xFF to 0x4A, 0xFF to 0x4B, 0x0F to 0x4C, 0x00 to 0x4D, and 0xFF to 0xF1-0xF5.
  7. Write the qual mask. These are in 0x3F, 0x40, 0x41, 0x42, 0x43 and 0xE7, 0xE8, 0xE9, 0xEA, 0xEB. They should all be set to 0xFF.
  8. ** Run a check to make sure that the eye scanner is aligned! ** See below.
  9. RMW the vertical offset. These are bits [10:0] in 0x97, although they map weird. Scanning from 0 to 508 in steps of 4 is probably fine?
  10. RMW the horizontal offset. These are bits [15:4] in 0x4F. These are signed values, with a range from -32RATE to +32RATE. Note that this means you should never set values greater than 512 or less than -512.
  11. RMW 0x3C bits [15:10] = 6'h1. This does not put the FSM in RESET like the above link says, it puts the FSM in "RUN".
  12. Poll 0x253 bits [3:0] until it is 4'h5 (this corresponds to the DONE bit set and state = END).
  13. Read the errors (0x251) and number of samples (0x252). Divide errors by number of samples * PRESCALE. Note that the eyescan runs until either counter saturates, and a "sample" corresponds to "line rate / bit width", I think.
  14. RMW 0x3C bits [15:10] = 6'h0.

Then repeat from step 9 with a new vertical and horizontal offset.

Realign the scanner

See https://adaptivesupport.amd.com/s/article/70872?language=en_US Run a check with the vertoffset = 0 and horizoffset = 0 and a very short prescale (like 5). If there are errors, the eye scanner is misaligned!

  1. RMW 0x880 to the horizontal offset.
  2. Set EYESCANRESET = 1
  3. RMW 0x800 to the horizontal offset.
  4. Set EYESCANRESET = 0.

Try again. Once you get no errors, the scanner is aligned and you're done.

Waveform view

https://adamwalker.github.io/Xilinx-Transceiver-Waveforms/