Collection of various notes regarding the Xilinx DSPs. Typically restricted to DSP48E2's.

DSP speed capabilities

At 375 MHz, we can:

(Barely!!) Internally registered inputs (AREG/BREG/DREG), through preadder, through multiplier, to PREG. This is exceptionally tight and only works with a direct input clock. Even adding the jitter from an MMCM is too much. 2 cascaded DSPs added together with inputs at least at preadder (or preadder bypassed). Cannot do 3: that probably only works at ~350 MHz (with MREG). Note also that AREG/BREG/DREG aren't that necessary: the routes from nearby FFs to DSPs are fast, and in fact fabric FFs + route to DSPs are surprisingly close to the clock-to-out times of the internal registers. FF to preadd registers is probably 1.421 ns, with huge margin at 375 MHz. So don't be afraid of AREG=0/BREG=0/DREG=0 in favor of PREADD_REG. Passing through the multiplier costs like another 0.7 ns.

DSP preadder capabilities

Note that the preadder options do not have a way of adding A+B in the preadder, so only one of 2 inputs can be cascaded between DSPs no matter what. There's just no way to do it (this is still a limitation in the Versal series too).