Home - barawn/verilog-library-barawn GitHub Wiki
Welcome to the verilog-library-barawn wiki!
Note: I created this Wiki to have a place to write FPGA tips/tricks that might be scattered across several projects. Generally I can't put all the tips/tricks for how to do things in modules, because there might be some Awesome Trick for doing something with like, 5 bit input width or something but parameterizing that is a giant pain in the neck. So it's easier to just write the ideas here so I don't forget.