Home - azonenberg/openfpga GitHub Wiki
Welcome to the open FPGA tools wiki!
Note: This project is NOT affiliated with OpenFPGA INC.
List of sub-projects and status (alphabetical)
| Device/Vendor | Status | Note |
|---|---|---|
| [Cypress PSoC 5(LP)/4/3](/azonenberg/openfpga/wiki/Cypress-PSoC) | Not yet started | Other than the UDB routing fabric and the DSI, everything is publicly documented. |
| [Silego Greenpak 4/5](/azonenberg/openfpga/wiki/Silego-GreenPak) | Can go from HDL to bitstream for most digital functions and some analog of SLG46620V | Bitstream is publicly documented |
| Xilinx CoolRunner-II | Everything understood for XC2C32A, larger devices missing ZIA table, working place-and-route | Needs a lot more bug testing |
| Xilinx 7 series | Wishlist, no actual work done |
Collected Research
Other open FPGA toolchain projects
TODO: List other projects here to avoid duplicating work
| Project | Description |
|---|---|
| Yosys | Open Verilog synthesis for a number of FPGAs |
| arachne-pnr | Place-and-route for iCE40 FPGAs |
| IceStorm | Bitstream manipulation tools for iCE40 FPGAs |
| fpgatools | FPGA toolchain for xc6slx9 |
| fpgalivereprog | full dynamic partial live reconfiguration for xc6slx9 FPGA: spec, blog |
| torc | Tools for Open Reconfigurable Computing paper [PDF] thesis [PDF] |
| debit | From the bitstream to the netlist: paper [PDF] |