The Trenz Electronic TEI0023 is a commercial-grade, low cost and small size module integrated with Intel^® MAX^® 10. Intel^® MAX^® 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Refer to http://trenz.org/tei0023-info for the current online version of this manual and other available documentation.

• Intel^® MAX^® 10 Commercial [10M08SAU169C8G]
  • Package: UBGA-169
  • Speed Grade: C8 (Slowest)
  • Temperature: 0°C to 85°C
  • Package compatible device 10M02...10M16 as assembly variant on request possible
• SDRAM Memory up to 64Mb, 166MHz
• Dual High Speed USB to Multipurpose UART/FIFO IC
• 64 Mb Quad SPI Flash - Not on all variants
• 4Kb EEPROM Memory
• 8x User LED
• Micro USB2 Receptacle 90
• 18 Bit 2MSPS Analog to Digital Converter
• 2x SMA Female Connector
• I/O interface: 23x GPIO
• Power Supply:
  • 5V
• Dimension: 86.5mm x 25mm
• Others:
  • Fully-Differential Programmable-Gain Instrumentation Amplifier

1. SMA Connector, J5...6
2. Amplifier, U12
3. Series Voltage Reference, U8
4. Analog to Digital Converter, U6
5. Voltage Regulator, U4 - U10 - U13 - U16
6. Switching Voltage Regulator, U11
7. SDRAM Memory, U2
8. Intel^® MAX^® 10, U1
9. SPI Flash Memory, U5
10. Oscillator, U7 - U19
11. FTDI USB2 to JTAG/UART adapter, U3
12. User LEDs, D2...9
13. FTDI configuration EEPROM, U9
14. Configuration/Status LED (Red), D10
15. Power-on LED (Green), D1
16. Push button, S1...2
17. Micro USB Connector, J9
18. 1x14 pin header, J2 (Not assembled)
19. 1x6 pin header, J4 (Not assembled)
20. 1x4 Header, J3 (Not assembled)
21. 1x14 pin header, J1 (Not assembled)

Storage device name	Content	Notes
Quad SPI Flash	Not Programmed
EEPROM	Programmed	FTDI configuration
SDRAM	Not Programmed

Table: Initial delivery state of programmable devices on the module

The FPGA configuration for Intel^® MAX^® 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel^® MAX^® 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.

Reset process must be done by pressing push button S1.

Signal	Push Button	Pin Header	Note
RESET	S1	J2	Connected to nCONFIG

Table: Boot process

FPGA Bank	Connector Designator	I/O Signal Count	Voltage Level	Notes
Bank 1A	J1	7	3.3V	AIN0...6
Bank 1B	J4	5	3.3V	JTAG interface
Bank 2	J1	4	3.3V	DIO2...5
Bank 5	J2	9	3.3V	DIO6...14
	J1	2	3.3V	DIO0...1
Bank 8	J2	1	3.3V	RESET

Table: General I/Os to Pin Headers and connectors information

FPGA Bank	I/O Signal Count	Connected to	Notes
Bank 1A	7	1x14 Pin header, J1	AIN0...6
	1	Jumper, J3	AIN7
Bank 1B	5	1x6 Pin header, J4	JTAG_EN, TDI, TDO, TMS, TCK
Bank 2	1	12MHz Oscillator, U7	CLK12M
	4	1x14 Pin header, J1	D2...5
	4	A2D, U6	ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
	3	Amplifier, U12	AMP_A0, AMP_A1, AMP_A2
	1	A2D, U6	ADC_PWR_EN1
	1	100MHz Oscillator, U19	CLK_EN
Bank 3	22	SDRAM, U2	RAM_ADDR_CMD
	1	A2D, U6	PDB_AMP
Bank 5	9	1x14 Pin header, J2	DIO6...14
	2	1x14 Pin header, J1	DIO0...1
	1	D12_R	DIO12
Bank 6	16	SDRAM, U2	DQ0...15
	2	SDRAM, U2	DQM0...1
	1	D11_R	DIO11
	1	A2D, U6	PDB_REF
Bank 8	8	User Red LEDs, D2...9	LED1...8
	6	SPI Flash, U5	F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn
	1	Red LED, D10	CONF_DONE
	6	FTDI JTAG/UART Adapter, U3	BDBUS0...5
	1	Push Button, S2	USER_BTN

Table: FPGA I/O Banks

The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.

Pins	Connected to	Note
VBUS	USB_VBUS
D+	FTDI FT2232H U3, DP pin
D-	FTDI FT2232H U3, DM pin

Table: Micro USB-2 connector pins

JTAG access to the TEI0023 FPGA through pin header connector J4.

JTAG Signal	Pin Header Connector	Note
TMS	J4-6
TDI	J4-5
TDO	J4-4
TCK	J4-3
JTAG_EN	J4-2	Pulled-up to 3.3V

Table: JTAG pins connection

Test Point	Signal	Connected to	Notes
TP1	+1.8 V	V_Lin, U13 ↔ A2D, U12
TP2	VREF_OUT	V_Lin, U8 ↔ A2D, U6
TP6	+14V_A	V_Lin, U10 ↔ Amplifier, U12
TP7	-14V_A	V_Lin, U10 ↔ Amplifier, U12
TP8	+14.5V	V_Switch, U11 / D11 ↔ L6 / V_Lin u10
TP9	-14.5V	V_Switch, U11 / L12 ↔ L7 / V_Lin u10
TP10	+5V5_A	u16 ↔ V_Lin, U8 / A2D, U12

Table: Test Points Information

Chip/Interface	Designator	Notes
SDRAM	U2
FTDI FT2232H	U3	JTAG/UART Adapter
SPI Flash	U5
EEPROM	U9
Oscillator	U7	12 MHz clock source
ADC	U12	Analog to Digital Converter
Push Buttons	S1...2
8x User LEDs	D2...9	Red LEDs

Table: On board peripherals

TEI0023 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

SDRAM I/O Signals	Signal Schematic Name	Connected to	Notes
Address inputs	A0 ... A13	bank 3	-
Bank address inputs	BA0 / BA1	bank 3	-
Data input/output	DQ0 ... DQ15	bank 6	-
Data mask	DQM0 ... DQM1	bank 6	-
Clock	CLK	bank 3	-
Control Signals	CS	bank 3	Chip select
	CKE	bank 3	Clock enable
	RAS	bank 3	Row Address Strobe
	CAS	bank 3	Column Address Strobe
	WE	bank 3	Write Enable

Table: SDRAM interface IOs and pins

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip. FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

FTDI Chip U3 Pin	Signal Schematic Name	Connected to	Notes
ADBUS0	TCK	FPGA bank 1B, pin G2	JTAG interface
ADBUS1	TDI	FPGA bank 1B, pin F5
ADBUS2	TDO	FPGA bank 1B, pin F6
ADBUS3	TMS	FPGA bank 1B, pin G1
BDBUS0	BDBUS0	FPGA bank 8, pin A4	User configurable
BDBUS1	BDBUS1	FPGA bank 8, pin B4	User configurable
BDBUS2	BDBUS2	FPGA bank 8, pin B5	User configurable
BDBUS3	BDBUS3	FPGA bank 8, pin A6	User configurable
BDBUS4	BDBUS4	FPGA bank 8, pin B6	User configurable
BDBUS5	BDBUS5	FPGA bank 8, pin A7	User configurable
BDBUS6	BDBUS6	FPGA bank 6, pin C11	User configurable
BDBUS7	BDBUS7	FPGA bank 3, pin J7	User configurable
BCBUS0	BDBUS0	FPGA bank 5, pin J9	User configurable
BCBUS1	BCBUS1	FPGA bank 3, pin K5	User configurable
BCBUS2	BCBUS2	FPGA bank 3, pin L4	User configurable
BCBUS3	BCBUS3	FPGA bank 3, pin L5	User configurable
BCBUS4	BCBUS4	FPGA bank 3, pin N12	User configurable

Table: FTDI chip interfaces and pins

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non-volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

Signal Schematic Name	Connected to	Notes
F_CS	FPGA bank 8, pin B3	Chip select
F_CLK	FPGA bank 8, pin A3	Clock
F_DI	FPGA bank 8, pin A2	Data in / out
nSTATUS	FPGA bank 8, pin C4	Data in / out, configuration dual-purpose pin of FPGA
DEVCLRN	FPGA bank 8, pin B9	Data in / out, configuration dual-purpose pin of FPGA
F_DO	FPGA bank 8, pin B2	Data in / out

Table: Quad SPI Flash memory interface

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

Schematic	Connected to	Notes
EECS	FTDI U3, Pin EECS
EECLK	FTDI U3, Pin EECLK
EEDATA	FTDI U3, Pin EEDATA

Table: I2C EEPROM interface MIOs and pins

The TEI0023 board is equipped with the Analog Devices ADAQ4003BBCZ 18-bit 2MSPS ADC.

Pins	Connected to	Notes
IN+	Instrumentation Amplifier U14, VOUT-
IN-	Instrumentation Amplifier U14, VOUT+
SDI	FPGA, Bank 2, pin M2, ADC_SDI
SDO	FPGA, Bank 2, pin M1, ADC_SDO
SCK	FPGA, Bank 2, pin N3, ADC_SCK
CNV	FPGA, bank 2, pin N2, ADC_CNV

Table: A2D converter interface and pins

Designator	Color	Connected to	Active Level	Note
D2...9	Red	LED1...8	Active High	User LEDs
D10	Red	CONF_DONE	Active Low	Configuration DONE LED
D1	Green	3.3V	Active High	After power on it will be on

Table: On-board LEDs

Designator	Connected to	Functionality	Note
S1	RESET	General reset
S2	USER_BTN	User push button	Connected to FPGA Bank 8

Table: On-board Push Buttons

Clock Source	Schematic Name	Frequency	Note
Microchip MEMS Oscillator, U7	CLK12M	12.00 MHz	Connected to FTDI FT2232 U3, pin 3. Connected to FPGA bank 2, pin H6.

Table: Oscillators

To power-up the module, power supply with minimum current capability of 1A is recommended.

FPGA	Typical Current
Intel® MAX® 10 10M08 FPGA SoC	TBD*

Table: Power Consumption

• TBD - To Be Determined

Actual power consumption depends on the FPGA design and ambient temperature.

Figure: Power Distribution

There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.

Power Rail Name	Connector J2 Pin	Connector J9 Pin	Direction	Notes
VIN	J2-13	-	Input	5 V - Pin Header
3.3V	J2-12	-	Output
5V	J2-14	-	Output
USB_VBUS	-	J9-1	Input	5 V - USB Connector

Table: Module power rails

Bank	Schematic Name	Voltage	Notes
Bank 1A	VCCIO1A	3.3V
Bank 1B	VCCIO1B	3.3V
Bank 2	VCCIO2	3.3V
Bank 3	VCCIO3	3.3V
Bank 5	VCCIO5	3.3V
Bank 6	VCCIO6	3.3V
Bank 8	VCCIO8	3.3V

Table: Intel^® MAX^® 10 SoC bank voltages

Symbols	Description	Min	Max	Unit	Reference Document
VIN	Supply voltage	4.75	5.25	V
CH1-, CH1+	Analog input voltage on amplifier U12 pin 1, 10	-20	20	V	LTC6373 datasheet
T_STG	Storage Temperature	-65	+125	°C

Table: Absolute maximum ratings

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Symbols	Min	Max	Unit	Reference Document
VIN supply voltage (5.0V nominal)	4.75	5.25	V
Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)	-10	10	V	LTC6373 datasheet
T_OP	0	+85	°C	10M08SAU169C8G datasheet

Table: Recommended operating conditions

Module size: 25 mm × 86.5 mm. Please download the assembly diagram for exact numbers.

PCB thickness: 1.598 mm.