First method

This simple example shows how to instantiate a tri-state buffer in Verilog HDL using the keyword bufif1.

module Tristate (in, oe, out);

    input   in, oe;
    output  out;
    tri     out;

    bufif1 b1 (out, in, oe);

endmodule

Second method

The following figure shows a tristate element using combinatorial process and always block.

The following table shows pin definitions for a tristate element using combinatorial process and always block.

IO Pins	Description
out_	Data Output (active Low)
outEnable	Output Enable
dataInput	Data Input

Following is Verilog code for a tristate element using a combinatorial process and always block.

See Here!

module TristatesBuf (
    out_,// Output (Active Low)
    outEnable, //Data Input
    dataInput//Output Enable
    ); 
    
    input dataInput, outEnable; 
    output out_; 
    reg out_; //Use for left hand side (LHS) of signals assigned inside in always blocks
    
    always @(dataInput or outEnable) 
    begin 
        if (outEnable)
        begin
           out_ = ~dataInput; 
        end else begin
          out_ = 1'bZ;
        end 
    end

endmodule