SR flip Flop with clear and preset - amirrezatav/Verilog_VHDL GitHub Wiki

SR Flip-Flop with clear and preset

Truth Table

Preset

Clear

Verilog Implementation

See Here !

        // SR Flip-Flop with  Preset and Clear
        module SRFF (
            out, // Q
            out_, // ~Q
            Set, // S
            Reset,// R
            CLR_,// clear
            PRE_,// Preset
            CLK_ // Clock
        );
            input Set , Reset , PRE_ , CLR_ , CLK_;
            output out , out_ ;
            nand(w1,Set,CLK_);
            nand(w2,Reset,CLK_);
            nand(out,w1,out_,PRE_);
            nand(out_,w2,out,CLR_);
        endmodule