Blocking and Nonblocking Statements - amirrezatav/Verilog_VHDL GitHub Wiki

Blocking Statements:

A blocking statement must be executed before the execution of the statements that follow it in a sequential block. In the example below the first time statement to get executed is a = b followed by

in Persian : باید به تریب اجرا شوند

Nonblocking Statements:

Nonblocking statements allow you to schedule assignments without blocking the procedural flow. You can use the nonblocking procedural statement whenever you want to make several register assignments within the same time step without regard to order or dependence upon each other. It means that nonblocking statements resemble actual hardware more than blocking assignments.

in Persian : با هم اجرا می شوند

  module block_nonblock();
  reg a, b, c, d , e, f ;
  
  // Blocking assignments
  initial begin
    a = #10 1'b1;// The simulator assigns 1 to a at time 10
    b = #20 1'b0;// The simulator assigns 0 to b at time 30
    c = #40 1'b1;// The simulator assigns 1 to c at time 70
  end
  
  // Nonblocking assignments
  initial begin
    d <=  #10  1'b1;// The simulator assigns 1 to d at time 10
    e <=  #20  1'b0;// The simulator assigns 0 to e at time 20
   f  <=  #40  1'b1;// The simulator assigns 1 to f at time 40
  end
    
  endmodule

Example - Blocking

module blocking (clk,a,c);
input clk;
input a;
output c;
 
wire clk;
wire a;
reg c;
reg b;

always @ (posedge clk )
begin
 b = a;
 c = b;
end

endmodule

Synthesis Output

Example - Nonblocking

module nonblocking (clk,a,c);
input clk;
input a;
output c;

wire clk;
wire a;
reg c;
reg b;

always @ (posedge clk )
begin
  b <= a;
  c <= b;
end

endmodule

Synthesis Output