Strategies to meet timing for complex systems

• Emulate a seed value with set_property LOC a register (1st stage of a rst reg) and generate several runs runs to expect at least 1 run without timing

• Use incremental compilation with the timing-free routed DCP as a hint for vivado

  • https://docs.amd.com/r/en-US/ug949-vivado-design-methodology/Using-Incremental-Implementation-Flows

• Iterative flow with phys_opt_design (not tiny failing timing)

  • https://docs.amd.com/r/en-US/ug949-vivado-design-methodology/Iterative-Flows
  • might be only for non-project flow but can be possible at the end of a project flow (must try)
  • phys_opt_design -directive AggressiveFanoutOpt then phys_opt_design -directive AlternateFlowWithRetiming

• Manual LOC/BEL of the critical logic

  • Compile with less logic to get at least 1 compile without timing for these modules.
  • Extract all the LOC/BEL of the regs, bram, dsp and apply them.
    • get_sites ... and use TCL to generate the set_property LOC/BEL
    • Select the cells you want to keep, remove all but selected with Tools->Floorplanning->Clear placement then File->Export->Constraints
  • Add dont_touch if necessary, include or ignore the replicated regs, add BEL/LOC of LUTs as well.
  • Run out-of-context synthesis for that modules to keep the netlist between runs (then you can also fix the LUTs, MUXes...)

• List the cells: show_objects [get_cells ...] use -name mylist to get a tap with information in the GUI

• Highlight the cells/nets/...: select_objects [get_cells ...]

• report utilization based on filter (selected cells): report_utilization -cells [get_selected_objects ]

• Add optimization options to opt_design: https://docs.amd.com/r/en-US/ug904-vivado-implementation/Available-Logic-Optimizations

  • -renamp to merge LUTs

• UG904: https://docs.amd.com/r/en-US/ug904-vivado-implementation/Preparing-for-Implementation