ZedBoard: Overview - alex-aleyan/xilinx GitHub Wiki

Table of Contents

Study Plan - review the documents below in the next order:

  1. glance thru these docs first:
  2. Start with this doc along with the schematic.
  3. Start working on this tutorials along with reading (4):
  4. This book is long, so read it in parallel with (3):
  5. Another good tutorial - https://www.beyond-circuits.com/wordpress/tutorial/

Links:

Features

  • Zynq®-7000 All Programmable SoC Artix-7: XC7Z020-CLG484-1
    • ARM dual-core Cortex A9 MPCores Processing System (PS; HPS Hard Processor System)
    • 7 series 85K PLs (Programmable Logic Cells ; FPGA).
  • Configuration/Debug:
    • Pnbpard USB-JTAG interface.
    • Xilinx Platform Cable JTAG connector.
  • Memory:
    • 512 MB DDR3
    • 256 Mb Quad-SPI Flash
    • 4 GB SD card
  • Communication:
    • Onboard USB-JTAG Programming
    • 10/100/1000 Ethernet
    • USB OTG (On The Go) 2.0
    • USB-UART
  • IO & Expansion Connectors:
    • FMC-LPC connector (68 single-ended, or 34 differential IOs)
    • Pmod™ 2x6 Compatible (Qt: 5),
    • XADC
    • 8 user LEDs
    • 7 push buttons
    • 8 DIP Switches
    • PS & PL I/O expansion
  • I2S Audio CODEC
  • Multiple displays
    • HDMI 1080p60 with 16-bit, YCbCr, 4:2:2 mode color
    • 8-bit VGA
    • 128 x 32 OLED)
  • Clock
    • 33.33333 MHz Clock source for PS
    • 100 MHz oscillator for PL

HPS vs FPGA Peripherals:

https://github.com/alex-aleyan/xilinx/blob/master/zedboard/figures/hps_fpga_block_diagram.PNG https://github.com/alex-aleyan/xilinx/blob/master/zedboard/figures/hps_fpga_block_diagram_detailed.PNG

  • HPS:
    1. 512 MB DDR3
    2. Reset
    3. Clock
  • HPS Multiplexed IS (MIO):
    1. QSPI Flash.
    2. SD Card.
    3. Gb Ethernet.
    4. USB OTG
    5. USB UART
    6. Pmod Compatible
    7. LED
    8. Switches
  • FPGA:
    1. Pmod Compatible (4)
    2. FMC (LPC)
    3. Audio CODEC
    4. HDMI Out
    5. VGA
    6. 128x32 OLED
    7. Clocl
    8. XADC
    9. LEDs
    10. Switches
    11. PROG SW
    12. DONE LED
    13. JTAG
Ref Designator Description Default Setting Function
JP1 Microphone Input Bias Open – No Electret Microphone Short to enable Bias Voltage for Electret Microphone. Right Channel only
JP2 Vbus 5V Enable Open – 5V Disconnected Short to enable 5V output to USB OTG Connector, J13, for either Host or OTG modes.
JP3 USB Vbus Capacitor Setting Open – Device Mode Short for Host mode (>120uF). Open for Device or OTG modes (4.7uF).
JP4 CFGBVS Select Not Populated Pre-configuration I/O standard type for the dedicated configuration bank 0. Vcco_0 is 3.3V, Connected to 3.3V through a 10K resistor. This jumper connects to GND and should NOT be used.
JP5 PUDC Select Not Populated Active Low input enables internal pull-ups during configuration on all SelectIO pins. Connected to Vadj through 10K resistor.
JP6 PS_MIO0 Pull-Down Short Install for SD Card boot on CES silicon.
JP7 Boot_Mode[3]/MIO[2] GND – Cascaded JTAG, 3.3 - Independent JTAG JTAG Mode. GND cascades PS and PL JTAG chains. VCC makes JTAG chains independent.
JP10,JP9,JP8, Boot_Mode[0]/MIO[5],Boot_Mode[2]/MIO[4],Boot_Mode[1]/MIO[3] 000 - JTAG, 100 – SD Card, 110-SDcard Boot Device Select See Zynq [Configuration Modes](add link here)
JP11 Boot_Mode[4]/MIO[6] GND – PLL Used PLL Select. GND uses PS PLLs. VCC bypasses internal PS PLLs
JP12 XADC Ferrite Bead Disable Open Short bypasses XADC-GND ferrite bead connection to board GND.
JP13 JTAG PS-RST Open Short connects JTAG PROG-RST to PS Reset.
J18 Vadj Select 1.8V Selects Vadj
Xilinx TRM MIO[6]Boot_Mode[4] MIO[5]Boot_Mode[0] MIO[4]Boot_Mode[2] MIO[3]Boot_Mode[1] MIO[2]Boot_Mode[3]
Cascaded JTAG 0
Independent JTAG 1
JTAG 0 0 0
Quad-SPI 1 0 0
SD Card 1 1 0
PLL Used 0
PLL Bypassed 1
MIO Bank 500 3.3V
MIO Bank 501 1.8V
Bank Voltage (default)
PS-Side
MIO Bank 0/500 3.3V
MIO Bank 1/501 1.8V
DDR 1.5V
PL-Side
Bank 0 3.3V
Bank 13 3.3V
Bank 33 3.3V
Bank 34 Vadj (2.5V)
Bank 35 Vadj (2.5V)

Constraints:

Pin Cosntraints:

zedboard_master_XDC_RevC_D_v3.xdc

Clock Cosntraints:

Pmod Modules