ZedBoard Tutorial: Zynq Workshop for Beginners - alex-aleyan/xilinx GitHub Wiki

Table of Contents

Standalone UART to PS (HPS):

References:

Setting up your environment:

  • Forget about windows. For some reason, Xilinx SDK has been struggling to find my hardware in Windows. Instead, do everything on CentOS. In VirtualBox settings for your guest OS:
    • Enable USB Controller as USB 3.0 9xHCI) Controller
    • Hijack 2012 Cypress Semiconductor Cypress-USB2UART-Ver1.0g
    • Hijack Digilent USB Device[0900]
  • When booting, make sure the ZedBoard PROG(J17) and UART (J14) cables are plugged in to your PC.
  • ISSUE: When running Vivado, make sure to launch with as sudo and the board powered up and conneccted - otherwise the programmer does not see the board (FIXME: figure out why)
  • Check if cable drivers are installed and install the drivers if not (source):
    • lsusb | grep future
    • sudo <PATH_TO_VIVADO_INSTALLATION>/Vivado/<VERSION>/data/xicom/cable_drivers/lin64/install_script/install_drivers/install_drivers

Exercise 1 - Getting something (anything!) working

  • Listing all board configurations regsub -all {\s+} [ get_board_parts ] \n
  • PS on FPGA.
    • FIXME: provide two method:
      • via automated script (vivado -mode batch -source do_build.tcl).
      • via manual procedure.
    • Flow Navigator->Open Implemented Design (Gotta open Implemented Design before Exporting Hardware).
    • File->Export-> Export Hardware
      • write_hwdef -force -file /opt/usr/admin/gitrepos/xilinx/zedboard/devel/projects/Zynq_ZedBoard_Vivado_Workshop/exerise_01/build_201007_131528/zedboard_base_proj.sdk/zedboard_top.hdf
  • SDK Part
    • File->Launch SDK
    • File->New->Board Support Package
    • File->New->Application Project
    • SK Terminal -> + -> /dev/ttyACM0
    • Xilinx -> Program FPGA
    • Run -> Run As -> Launch On Hardware
    • Load software

Exercise 2

Same as Exercise01 but replace the content of helloworld.c with:

#include <stdio.h>
#include "platform.h"

#include "xgpiops.h"
#include "xparameters.h"

int main()
{
    // typedef struct {
    // 	   u16 DeviceId;		/**< Unique ID of device */
    // 	   u32 BaseAddr;		/**< Register base address */
    // } XGpioPs_Config;

    XGpioPs_Config * xgpio_config_p ;

    // typedef struct {
    // 	   XGpioPs_Config  GpioConfig;	 /**< Device configuration */
    // 	   u32             IsReady;		 /**< Device is initialized and ready */
    // 	   XGpioPs_Handler Handler;	     /**< Status handlers for all banks */
    // 	   void            *CallBackRef; /**< Callback ref for bank handlers */
    // 	   u32             Platform;	 /**< Platform data */
    // 	   u32             MaxPinNum;	 /**< Max pins in the GPIO device */
    // 	   u8              MaxBanks;	 /**< Max banks in a GPIO device */
    //     u32             PmcGpio;      /**< Flag for accessing PS GPIO for versal*/
    // } XGpioPs;

    XGpioPs xgpiops_p ;

    int status, led = 0;

    init_platform();

    printf("Hello World\n\r");

    xgpio_config_p = XGpioPs_LookupConfig(XPAR_PS7_GPIO_0_DEVICE_ID);

    //status = XGpioPs_CfgInitialize(&xgpiops_p, xgpio_config_p, xgpio_config_p->BaseAddr);
    status = XGpioPs_CfgInitialize(&xgpiops_p, xgpio_config_p, (*xgpio_config_p).BaseAddr);

    XGpioPs_SetDirectionPin( &xgpiops_p, 7, 1) ;

    while(1){
            for (int count=0; count < 20000000; count++){}
            XGpioPs_WritePin( &xgpiops_p, 7, 0 );
            for (int count=0; count < 20000000; count++){}
            XGpioPs_WritePin( &xgpiops_p, 7, 1 );
            printf("Hello World\n\r");
    }
    //cleanup_platform();
    return 0;
}

Exercise 3

  • Start with exercise 2

Exercise 4

# LED and SW:
open_bd_design {/opt/usr/admin/gitrepos/xilinx/zedboard/devel/projects/Zynq_ZedBoard_Vivado_Workshop/exerise_04/build_current/zedboard_ex01.srcs/sources_1/bd/design_1/design_1.bd}

#set_property -dict [list CONFIG.PCW_USE_M_AXI_GP0 {1}] [get_bd_cells processing_system7_0]
#set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1} CONFIG.PCW_IRQ_F2P_INTR {1}] [get_bd_cells processing_system7_0]
set_property -dict [list CONFIG.PCW_USE_M_AXI_GP0 {1} CONFIG.PCW_USE_FABRIC_INTERRUPT {1} CONFIG.PCW_IRQ_F2P_INTR {1}] [get_bd_cells processing_system7_0]

create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0

set_property location {2.5 746 178} [get_bd_cells axi_gpio_0]
set_property location {2.5 868 190} [get_bd_cells axi_gpio_0]
set_property -dict [list CONFIG.C_GPIO_WIDTH {8} CONFIG.C_GPIO2_WIDTH {8} CONFIG.C_IS_DUAL {1} CONFIG.C_ALL_INPUTS {1} CONFIG.C_ALL_OUTPUTS_2 {1}] [get_bd_cells axi_gpio_0]

apply_bd_automation -rule xilinx.com:bd_rule:axi4 -config { Clk_master {/processing_system7_0/FCLK_CLK0 (100 MHz)} Clk_slave {Auto} Clk_xbar {Auto} Master {/processing_system7_0/M_AXI_GP0} Slave {/axi_gpio_0/S_AXI} intc_ip {New AXI Interconnect} master_apm {0}}  [get_bd_intf_pins axi_gpio_0/S_AXI]

apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {Custom} Manual_Source {Auto}}  [get_bd_intf_pins axi_gpio_0/GPIO]
apply_bd_automation -rule xilinx.com:bd_rule:board -config { Board_Interface {Custom} Manual_Source {Auto}}  [get_bd_intf_pins axi_gpio_0/GPIO2]

set_property name gpio_sw  [get_bd_intf_ports gpio_rtl]
set_property name gpio_led [get_bd_intf_ports gpio_rtl_0]

save_bd_design

make_wrapper -files [get_files /opt/usr/admin/gitrepos/xilinx/zedboard/devel/projects/Zynq_ZedBoard_Vivado_Workshop/exerise_04/build_current/zedboard_ex01.srcs/sources_1/bd/design_1/design_1.bd] -top

add_files -norecurse /opt/usr/admin/gitrepos/xilinx/zedboard/devel/projects/Zynq_ZedBoard_Vivado_Workshop/exerise_04/top.vhd
set_property top top [current_fileset]
update_compile_order -fileset sources_1

reset_run synth_1
reset_run design_1_processing_system7_0_0_synth_1
launch_runs impl_1 -to_step write_bitstream

Exercise 9 - Talking to external components

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