11 IOBs - alex-aleyan/xilinx GitHub Wiki

Sources:

• UG571 - Ultrascale SelectIO
• UG974 - Ultrascale Libraries
• UG949 - Design Methodology

Typical scenarios:

• Serial with Diff paris
  • Driving data ( o_ser_data -> OBUFDS(IOSTANDARD=LVDS_25) => O_SER_P|O_SER_N ):

    attribute IOB
    attribute IOB of o_ser : signal is "TRUE":
    
    obuf_out: OBUFDS
      generic map (IOSTANDARD => "LVDS_25")
      port map ( O  => o_ser_p,
                 OB => o_ser_n,
                 I  => o_ser );
    

  • Driving clock:

    
    oddr_swap_polarity <= '0' when gen_swap_polarity = false else 1'1;
    oddr_en <= fsm_oddr_en;
    
    oddr_clk_out: OBUFDS
      generic map (IOSTANDARD => "LVDS_25")
      port map ( c_ => i_clk_core
                 d1 => oddr_swap_polarity,
                 d2 => oddr_en,
                 ce => '1',
                 r => '0',
                 s => '0',
                 q  => o_clk   );
    
    obuf_clk_out: OBUFDS
      generic map (IOSTANDARD => "LVDS_25")
      port map ( I  => o_clk  ,
                 O  => o_clk_p,
                 OB => o_clk_n);
    

  • Receiving clock:

    ibufds_clk_in: IBUFDS
      generic map ( DIFF_TERM     => TRUE,
                    IBUF_LOW_PWR  => TRUE,
                    IOSTANDARD    => "LVDS_25")
      port map ( I  => i_clk_p,
                 IB => i_clk_n,
                 O  => i_clk_bufds);
    
    ibufr_clk_in: BUFR
      port map ( I   => i_clk_bufds,
                 O   => i_clk,
                 CE  => '1'  ,
                 CLR => '0' );
    

  • Receiving Data:

    attribute IOB
    attribute IOB of o_ser : signal is "TRUE":
    
    ibuf_in: IBUFDS
      generic map ( DIFF_TERM    => TRUE,
                    IBUF_LOW_PWR => TRUE,
                    IOSTANDARD   => "LVDS_25")
      port map ( I  => i_ser_data_p,
                 IB => i_ser_data_n,
                 O  => i_ser_data  );