10 GbT - alex-aleyan/xilinx GitHub Wiki

Resources

Overview:

  • OTN and OTN mapping, FlexE (Flex Ethernet) Interface,

  • GTR (6Gb) GTX (12.5Gb), GTH (16.3Gb), GTZ (28Gb), GTY (32Gb), GTM (58Gb-112Gb)

    • GTYE5

  • Supported Protocols:

    • PCIe:
      • Gen1 (2.5, 8b/10b), Gen2 (5, 8b/10b), Gen3 (8, 128b/130b).
      • Hard IP only: Integrated Block for PCIe (UltraScale arch).
      • Hard IP for Physical Layer PHY IP + Soft IP for PCIe MAC.
      • CPM block: The Versal devices can include an integrated block for PCle with DMA and cache coherent interconnect (CCIX):
    • Ethernet: Preamble (0x55), SFD, DA, SA, Length/Type, Payload, FCS, IFG.
    • Aurora: B2B and C2C, System Synch or Asynch.
    • Interlaken: C2C.
    • JESD204: C2C for interfacing ADCs and DACs.

  • Line modulation?:

    • PAM4 (GTM; 64/66, 128/130)
    • NRZ (GTY/GTYP; 64/66)

  • Layers:

    • PMD (Physical Medium Dependent): LASER and Connector.
    • PMA (Physical Medium Attachment): SERDES
      • OOB
      • PCIe
      • Pre/Post Emb
      • PISO (parallel in serial out block) takes parallel data and serializes it LSb first.
      • Clock Interpolator.
      • Transmit Driver.
    • PCS (Physical Coding Sublayer)
      • Encoder (8b/10b, 64b/66b, 128b/130b).
        • Review SYNC PREAMBLE (2-bit), TYPE (8-bit), CONTROL (7-bit), DATA (8-bit).
          • Sync Preamble:
            • 0b01: pure data
            • 0b10: type, control + data.
          • Control words:
            • 0xFB: /S/ Start, start of packet.
            • 0xFD: /T/ Terminate - end of packet.
            • 0x07 or 0x00: /l/ Idle - no payload available.
            • /E/ Error - error indication.
            • /Q/ Ordered sets - control and status words
      • Gearbox
      • Scrambler (64b/66b)
        • Scrambling of the payload provides adequate transition for clock recovery.
        • Handles DC bias problems.
      • CRC Generator
      • OOB Generator
      • PRBS (Pseudo Random Binary Sequence).
      • 64b/66b - line encoding scheme developed for 10 Gigabit Ethernet that uses a scrambling method combined with a non-scrambled sync pattern and control type.
        • Alignment:
          • sync value of 01 or 10 every 66 bits - finds frame alignment.
          • To speed lock time, alternative/optional protocols replace data with special training or locking sequences that can ease alignment.
    • MAC (Media Access Control)
      • Hard IP Cores:
        • MRMAC (FEC + PCS+MAC),
        • DCMAC (FEC + PCS+MAC)
    • PMA:

      • System Synchronous, Source Synchronous, Implicitly Synchronous.

      • GTHE3:

        • Clock sources:
          • 2 pairs of Dedicated Differential Clock Pins/Buffers:
            • GTREFCLK0 (IBUFDS_GTE3, OBUFDS_GTE3)
            • GTREFCLK1 (IBUFDS_GTE3, OBUFDS_GTE3)
          • One from within the fabric: GTGREFCLK.
          • Neighboring QPLLs: GTNORTHREFCLK0, GTNORTHREFCLK1, GTSOUTHREFCLK0, GTSOUTHREFCLK1
        • PLLs (Ring vs LC?):
          • 4 Channel PLL (CPLL; GTHE3_CHANNEL[0,1,2,3]):
            • range 2 to 6.25 GHz,
            • one per transceiver channel (four per transceiver quad).
          • 2 Quad PLLs (QPLL; GTHE3_COMMON) :
            • Two fractional LC PLLs per transceiver quad.
            • LC tanks with VCO frequency range
            • QPLL0: 9.8 to 16.3GHz; QPLL1: 8.0 to 13.0GHz
          • Neighboring QPPLs:
            • Two North QPPLs: GTNORTHREFCLK0, GTNORTHREFCLK1
            • Two south QPLLs: GTSOUTHREFCLK0, GTSOUTHREFCLK1

      • GTYE5_QUAD:

        • Clock sources/pins:
          • Dedicated Clock Pins/Buffers:
            • *_GTREFCLK0 (IBUFDS_GTE5, OBUFDS_GTE5).
            • *_GTREFCLK1 (IBUFDS_GTE5, OBUFDS_GTE5).
          • Neighbor’s QPLLs:
            • *_NORTHREFCLK0, *_NORTHREFCLK1,
            • *_SOUTHREFCLK0, *_SOUTHREFCLK1
          • One from within the fabric: *_GTGREFCLK.
          • Note that *_ is
            • HSCLK0_RPLL, HSCLK0_LC for HSCLK0 block
            • HSCLK1_RPLL, HSCLK1_LC for HSCLK1 block
        • xBUFDS_GTE5
          • one O output pin
          • one ODIV2 pin (O, O/2, 0, reserved)
        • PLLs (HSCLK0 block, and HSCLK1 block):
          • Two HSCLK blocks per GbT Quad
            • HSCLK0 for CHANNEL0 Xcvr and CHANNEL1 Xcvr
            • HSCLK1 for CHANNEL2 Xcvr and CHANNEL3 Xcvr
          • Each HSCLK block has:
            • One LCPLL (8GHz - 16GHz)
            • One RPLL (4GHz - 8GHz)