08 Buses - alex-aleyan/xilinx GitHub Wiki

References:

• AXI:
  • Mohammad S. Sadri YouTube channel
  • Mohammad S. Sadri - microelectronic systems design research group

Buses:

• UART
• I2C
• SPI
• PCIe
• System Buses
  • General Classification:
    • CPU Bus (Memory Mapped Bus)
    • Local Bus (Streaming or Memory Mapped Bus)
  • AXI (ARM)
    • Referecnes:
      • AXI GP vs AXI HP
    • Types:
      • Memory Mapped (Burst)
      • Memory Mapped Lite (No Burst)
      • Streaming
    • Topology:
      • AXI Master/Root
      • AXI Slave/Target/Leaf
      • AXI Interconnect/Arbitrator
  • WishBone (OpenCore IPs)
  • IBM Core-Connect (uncommon nowaday)
• CCIX (Cache Coherent Interconnect for Accelerators) - allows multiple CPUs share a common memory space via "hardware semaphorse":
  • https://www.youtube.com/watch?v=OUCf7twWzq0
  • https://www.synopsys.com/designware-ip/technical-bulletin/introduction-ccix-2017q3.html)
  • https://docs.xilinx.com/r/en-US/pg118-system-cache/CCIX-Example
  • https://www.xilinx.com/support/documents/architecture-manuals/am016-versal-cpm-ccix.pdf