HP I/O banks - designed to meet the performance requirements of high-speed memory and other chip-to-chip interfaces with voltages up to 1.8V.
HR I/O banks - designed to support a wider range of I/O standards with voltages
up to 3.3V.
HD I/O banks - designed to support low-speed interfaces.
See UltraScale Architecture and Product Overview (DS890) [Ref 3] documents the available number of each type of bank for all devices.
Kintex UltraScale and Virtex UltraScale have:
HP IO banks (Chapter: 1, 2).
HR IO banks (Chapter: 1, 2).
NOTE: Any references to Mobile Industry Processor Interface (MIPI) D-PHY or HD I/O in these chapters (Ch1, Ch2) do NOT apply to these devices.
Zynq UltraScale+, Kintex UltraScale+, and Virtex UltraScale+ have:
HP IO banks (Ch: 1, 2 , 3).
HD IO banks (Ch: 1, 2 , 3).
HP and HR IO Banks - supported features:
Each I/O bank contains 52 SelectIO interface pins.
UltraScale new features:
HR I/O mini-banks containing 26 SelectIO pins (with its own power supply and VREF pin)
pseudo-open-drain logic standards (POD).
Series output termination control is available in HP I/O banks (improves signal integrity and eases board design).
Internal VREF level scan (HP I/O banks only). One dedicated external VREF pin per bank.
Pre-emphasis (reduces inter-symbol interference and minimizes the effects of transmission line losses) is available for the DDR4 standard in HP I/O banks and the LVDS TX standard in HP/HR I/O banks.
Linear equalization on VREF-based receivers (in HP I/O banks) and differential receivers (HP/HR I/O banks) is available to overcome high-frequency losses through the transmission channel.
Receiver offset cancellation is available for some I/O standards to compensate for process variations (HP I/O banks only).
Digitally controlled impedance (DCI) is only available in HP I/O banks. DCI uses only one reference resistor per bank, 240Ω to GND on the VRP pin. The values of the driver or input termination are determined by the OUTPUT_IMPEDANCE and On-Die Termination (ODT) attributes, respectively.
VCCAUX_IO only supports a nominal voltage level of 1.8V.
A SLEW value of MEDIUM is supported in HP I/O banks
The DCITERMDISABLE port can control both DCI and non-DCI on-die input termination features in HP I/O banks
Where applicable, asserting IBUFDISABLE causes the input to the interconnect logic to be a 0. This is different from the resulting 1 after asserting IBUFDISABLE in 7 series devices.
The bit slice is effectively a physical layer (PHY) block that replaces and enhances the functionality of the Component mode primitives. This PHY block gives tighter control over timing and provides new features enabling higher data rate reception in UltraScale devices.
MIPI D-PHY transmitter and receiver functions are supported in the HP I/Os specific to the Virtex UltraScale+, Kintex UltraScale+, and Zynq UltraScale+ devices.
HD IO Banks and HP IO Banks contain configurable SelectIO interface receivers/drivers with these features:
programmable control of output strength and output slew rate.
provides power to the I/O circuitry (should be powered by 1.8V).
Vccint_io (internal supply for IO Banks).
State of I/Os During and After Configuration (Banks 0,65; Bank 60,70):
During configuration:
IO drivers are 3-states on all banks except Bank 0 and Bank 65 (Bank 60 and Bank 70 excluded as well on devices with multiple SLRs).
all HP I/O banks use the default IOSTANDARD = LVCMOS18, SLEW = FAST, and DRIVE = 12 mA setting.
Bank 0:
contains cofniguration pins dedicated to the configuration functions.
Bank 65 (multi-function, configuration bank):
contains multi-function IO pins which can be used for configuration and converted to programmable IO pins after configuration is complete.
Bank 60,70: devices with multiple Super Logic Regions (SLRs) utilize pins on Bank 60 and Bank 70 similarly to multi-function pins (see Bank 65).
DCI (Digitally Controlled Impedance):
DCI is only available in HP I/O banks (not available in HR I/O banks).
To terminate a trace, resistors are added to make the output and/or input match the impedance of the receiver or driver to the impedance of the trace.
PC board traces must be properly terminated to avoid reflections or ringing to achieve better signal integrity.
By placing the termination resistors as close as possible to the output driver or input buffer, DCI eleminates the need for termination resistor on the board which:
simplifies board routing.
reduces on the board component count.
eliminating stub reflection thus imrpoving signal integrity by .
DCI uses one multipurpose reference VRP pin in each IO bank to control the impedance value of either:
the driver for all of the I/Os of that bank.
the parallel-termination for all of the I/Os of that bank.
To matching the characteristic impedance of the transmission line, DCI can either:
control the output impedance of a driver,
or add a controlled parallel termination present at the receiver.
The value of the termination resistor is determined by
the ODT attribute for the controlled parallel termination of the receiver buffer.
the OUTPUT_IMPEDANCE attribute for the controlled impedance of the driver.
VRP pin:
For all DCI I/O standards, the external reference resistor (RVRP) should be terminated to GND using a 240Ω resistor.
each VRP pin requires a unique reference resistor.
DCI actively adjusts these impedances inside the I/O to calibrate to an external, precision reference resistor placed on the VRP pin.
Thus, compensating for changes in I/O impedance due to
process variation.
variations of temperature.
supply voltage fluctuations.
To utilize the DCI feature in the design:
Assing one of the DC IO standards in the HP IO Bank.
Connect the VRP multi-funcion pin to a precision resistor (240Ω) tied to GND.
To control the termination value, set:
the ODT attribute for all applicable I/Os with the controlled parallel terminations.
the OUTPUT_IMPEDANCE attribute for all applicable I/Os with the controlled impedance driver.
DCI cascading - allows cascading the VRP node for multiple IO banks on the same IO Bank Column, so that only one VRP pin is connected to a precision resistor (UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575)).
The guidelines when using DCI cascading are as follows:
DCI cascading is only available through a column of HP I/O banks
The master and slave SelectIO technology banks must all reside on the same HP I/O column on the device and can span the entire column unless there is an interposer boundary.
DCI cascading cannot pass through the interposer boundaries of the larger UltraScale devices with stacked silicon interconnect (SSI) technology
Master and slave I/O banks must have the same VCCO and VREF (if applicable) voltage.
I/O banks in the same HP I/O column that are not using DCI (pass-through banks) do not have to comply with the VCCO and VREF voltage rules for combining DCI settings.
DCI I/O banking compatibility rules must be satisfied across all master and slave banks.
To locate I/O banks that reside in the same I/O column, see the figures in the Die Level Bank Numbering Overview section of the UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG57
If the device temperatues vary significantly from the time the device is configured, the DCI calibration can be reset by instantiating the DCIRESET primitive:
Xilinx design primitive that provides the capability to perform a reset of the DCI controller state machine during normal operation of the design.
Toggling RST input to the DCIRESET primitive restarts the calibration process.
all IOs using DCI become unavailable until the LOCKED output from DCIRESET block is asserted.
halt the start-up sequence at the end of the device configuration sequence until the DCI logic has performed the first match (calibration) to the external reference resistor.
DCIUpdateMode Configuration Option:
overrides the control of how often the DCI circuit updates the impedance matching to the VRP reference resistor.
defaults to ASREQUIRED in the Xilinx implementation tools.
Values:
ASREQUIRED: Initial impedance calibration is made at device initialization, and dynamic impedance adjustments are made as needed throughout device operation (default).
QUIET: Impedance calibration is done once at device initialization, or each time the RST pin is asserted on the DCIRESET primitive for designs that include this primitive.
Must include and use the DCIRESET primitive in your design when using DCI IO standard (in HP I/O bank devices) on pins in IO Banks 65 (60,70 on devices with multiple SLRs.
Pulse RST intput to the DCIRESET primitive and wait for LOCKED signal to be asserted prior using IO configured as DCI standard.
This is required because these IO pins ignore the initial DCI calibration that happens during the normal device initialization (If DCIRESET was not used and DCIUpdateMode was set to QUIET, these pins would never have their DCI values set).