05 Memory - alex-aleyan/xilinx GitHub Wiki

Sources:

• DDR Memory Playlist
• https://www.systemverilog.io/ddr4-basics
• https://www.youtube.com/watch?v=kCmu5k6jfXM&list=PLQgOKy0AlWh9SfysI81pNwQVxzq6ROiN6
• "UG954 ZC706 eval board" contains good notes on DDR memory @ page 18 DDR3 SODIMM Memory (PL) - YouTube link
• DMA - Xilinx AXI DMA Product Guide

Terminology:

• CPU/Mother board level:
  • Memory Channel
  • DIMMS
• RAM Stick level:
  • Memory Ranks
• DDR4 IC level:
  • Bank Group
  • Bank Address
  • Row Address
  • Column Address
  • Data Bus/Strobe x2,x4,x8,x16
• Xilinx
  • distributed RAM (0.6 ~ 103Mb)
  • Block RAM (0.8Mb ~ 174Mb)
  • UltraRAM (6.8Mb ~ 717Mb)
  • High Bandwidth Memory (HBM; 4GB ~ 32GB)
  • Hard interface for External DDR4 (2133~2666 Transactions per Second or Mb/s).