04 Timing Closure Techniques, Timing Constraints, Multicycle Path Constraints - alex-aleyan/xilinx GitHub Wiki

Resources:

Notes:

  • Limit the nesting of the control constructs (if, else, for, when, case) to a depth greater than 5.
  • When performing comparisons
    • Keep in mind the LUT input sizes and keep the sizes in mind when implementing comparisons..
  • Counters:
    • Pay extra attention to counters when counting up and comparing to a particular value - counting down and comparing may yield better results.
    • Instead of incapsulating a counter and its comparison within your state machine, bring them out to a separate process/always block. Count and compare in this outside process and set the flag for the FSM once the counter reaches the desired value.
  • FSMs
    • never use large bus width comparisons - do it outside the FSM and have the FSM check the logic output via a flag.
    • never infer multiplexors in the next state or the output logic - implement the MUXs outside the FSM.
    • must contain RESET state (driven by synchronous reset on the same clock domain as the FSM is on).
    • make sure to provide the default values for the FF to avoid latches and resultant undetermined behaviour.
  • Floor planning (Device View)
    • Perform preliminary floor planning to allocate the primitive (DSP and such) appropriate close to the PINS these primitives will be getting the data from.

Multicycle Path