01 Sources - alex-aleyan/xilinx GitHub Wiki

YouTube Channels and Videos:

• Greg Stitt
• Greg Stitt's HUB
• Nandland
• XilinxInc
  • xilix.com/video
• cadencedesignsystems
• FPGAsforBeginners
• MohammadSSadri
• Alex Forencich
• BenEater

Forums:

• https://www.reddit.com/r/FPGA/comments/omrnrk/list_of_useful_links_for_beginners_and_veterans/
  • https://www.adiuvoengineering.com/blog
  • https://www.chipverify.com/verilog/verilog-tutorial
  • https://www.fpga4fun.com/
  • https://vhdlguide.readthedocs.io/en/latest/
  • https://www.joelw.id.au/FPGA/CheapFPGADevelopmentBoards

PCB/pins:

• https://www.youtube.com/watch?v=THLdycw9-Vs

Constraints:

• UG903 - Using Constraints
• UG945 - Vivado Design Suite Tutorial: using constraints

Clock Domain Crossings:

• Resources:
  • Coding Style
  • Cummings
    • Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog
    • http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
    • http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf
  • Crossing clock domains with an Asynchronous FIFO: https://zipcpu.com/blog/2018/07/06/afifo.html
  • http://www.verilab.com/files/sva_cdc_paper_dvcon2006.pdf
  • “Clock Domain Crossing Demystified: The Second Generation Solution for CDC Verification,”
  • http://en.wikipedia.org/wiki/Clock_Domain_Crossing_Verification - See references on this page!
  • Look into "Sunburst Design - Expert Clock Domain Crossing (CDC) & FIFO Design Techniques" TRAINING!
  • https://www.verilogpro.com/clock-domain-crossing-part-1/
  • https://systemverilogdesign.com/tag/cdc/
  • https://www.realintent.com/technical-papers/ - also see https://www.realintent.com/clock-domain-crossing-demystified/
  • https://semiwiki.com/eda/aldec/7344-clock-domain-crossing-in-fpga/
  • https://www.edn.com/synchronizer-techniques-for-multi-clock-domain-socs-fpgas/
  • https://web.stanford.edu/class/ee183/handouts/synchronization_pres.pdf
  • https://www.reddit.com/r/FPGA/comments/w4gydg/minimum_depth_of_a_cdc_fifo/
  • https://hardwarebee.com/clock-domain-crossing-techniques-for-fpga/
• Tools:
  • Synopsys SpyGlass
    • https://semiwiki.com/eda/synopsys/6794-cdc-verification-for-fpga-beyond-the-basics/
    • https://www.synopsys.com/verification/static-and-formal-verification/spyglass/spyglass-fpga.html
  • Xilinx
    • https://www.xilinx.com/video/hardware/cross-clock-domain-checking-cdc-analysis.html

Resets:

• Cummings
  • http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf
  • http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf
  • http://www.sunburst-design.com/papers/HunterSNUGSV_UVM_Resets_paper.pdf
• https://www.xilinx.com/support/documentation/white_papers/wp272.pdf
• https://www.eetimes.com/how-do-i-reset-my-fpga/#