altera tools installation - alex-aleyan/linux_wiki GitHub Wiki

VirtualBox Links:
https://download.virtualbox.org/virtualbox/5.2.8/
https://gist.github.com/larsar/1687725
https://www.tutorialspoint.com/virtualization2.0/virtualization2.0_virtualbox.htm
https://www.virtualbox.org/manual/
https://www.makeuseof.com/tag/how-to-use-virtualbox/

Altera Tools Links:
https://fpgawiki.intel.com/wiki/Quartus_for_Linux
http://insights.sigasi.com/tech/installing-quartus-64-bit-linux-system.html
https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd05302012_638.html
http://www.dmi.unict.it/~scollo/slidy/sd-2018/sd_e01/tips/QuartusInstall.txt
http://www.armadeus.org/wiki/index.php?title=Quartus_installation_on_Linux
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/quartus_unix.pdf
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/quartus_unix.pdf

install 32-bit libs and utils using the install_32bit_libs.sh before installing altera tools:

#!/bin/bash

install_these_libs=(
libc.i686
glibc.i686
libXext.i686
libX11.i686
libXau.i686
libXdmcp.i686
freetype.i686
fontconfig.i686
libpng.i686 
libSM.i686
expat.i686
libXft.i686
ncurses-libs.i686
libstdc++*
libstdc++*686
libpng12*
)

yum install ${install_these_libs[@]}

Also install these if RHEL7:

unixODBC-libs*i686
unixODBC*i686
ncurses*i686
ncurses-libs*i686
libzmq3*i686
libXext*i686
alsalib*i686
libXtst*i686
libXft*i686
libxml2*i686
libedit*i686
libX11*i686
libXi*i686

Install Quartus and rest of altera tools prior installing the Monitor Program!
1. Untar the Quartus-lite-16.1.2.203-linux.tar and run setup.sh (install to /opt/tools/intelFPGA_lite)
2. To fix the /bin/bash error, run this command sed -i -e 's/\r$//' /opt/tools/intelFPGA_lite/16.1/quartus/bin/up_hps

Installing Monitor Program:

Download the tar ball intel_fpga_upds_setup.tar
untar it using: tar -xvf 'intel_fpga_upds_setup.tar
Read these files first:
1. intel_fpga_upds_setup/readme.txt
2. intel_fpga_upds_setup/usb_blaster.txt

Add these environment variables to your bashrc (or /etc/profile or /etc/environemnt)

export ALTERA_DIR="/opt/tools/intelFPGA_lite/16.1"
export MODELSIM="${ALTERA_DIR}/modelsim_ase/modelsim.ini"
export QSYS_ROOTDIR="${ALTERA_DIR}/quartus/sopc_builder/bin"
export SOPC_KIT_NIOS2="${ALTERA_DIR}/nios2eds"
export QUARTUS_ROOTDIR="${ALTERA_DIR}/quartus"
export QUARTUS_ROOT_DIR_OVERRIDE="$QUARTUS_ROOTDIR"
export MONITOR_PROGRAM="$ALTERA_DIR/University_Program/Monitor_Program/bin"
export EMBEDDED_SHELL="$ALTERA_DIR/embedded"
export DS5="$ALTERA_DIR/embedded/ds-5/bin"

export PATH="$PATH:\
$QUARTUS_ROOT_DIR_OVERRIDE/bin:\
$ALTERA_DIR/modelsim_ase/bin:\
$SOPC_KIT_NIOS2/bin:\
$QSYS_ROOTDIR:\
$MONITOR_PROGRAM:\
$EMBEDDED_SHELL"

Run the installer

mkdir -p /opt/intel/intel_fpga_upds_setup/upds_installer_data
cp /media/sf_vm_shared_dir/intel_fpga_upds_setup.tar /opt/intel/intel_fpga_upds_setup/
cd /opt/intel/intel_fpga_upds_setup/
tar -xf intel_fpga_upds_setup.tar
cp /opt/intel/intel_fpga_upds_setup/upds_installer_data.tgz /opt/intel/intel_fpga_upds_setup/upds_installer_data
cd /opt/intel/intel_fpga_upds_setup/upds_installer_data
tar -xzf upds_installer_data.tgz

Installing Embedded Development Tools
1. Download SoCEDSSetup-16.1.0.196-linux.run
2. Run SoCEDSSetup-16.1.0.196-linux.run

To link multiple versions of the tool and to allow the user to choose the version:

Download the common repo into /opt/gitrepos/common

Set a symbolic link as follows:

cd /usr/local/bin
ln -s ../../../opt/gitrepos/common/scripts/setQuartusEnv.sh alteraSetEnv.ln

Add this line to your /etc/bashrc

export PATH="$PATH:/usr/local/bin"
export PATH_ORIG="$PATH"
source /opt/gitrepos/common/scripts/alterarc

Old Notes on Nios Terminal:

CLI commands:
Create a project in Quartus
In Quartus, open QSYS and add NIOS and other peripherals to the design.
Build the Firmware in Quartus to generate the .sof file.
Create a project in Eclipse.
Create NIOS BSP and NIOS Application.
Generate the BSP.
Build the NIOS BSP and NIOS Application to generate the .elf file.
Program the firmware into the chip using .sof file.
Program the software into the chip using .elf file.

quartus_map --read_settings_files=on --write_settings_files=off lab_4_part_2_b -c lab_4_part_2_b
	#Analysis and Synthesis which creates:
	#	lab_4_part_2_b.flow.rpt, 
	#	lab_4_part_2_b.map.rpt,
	#	lab_4_part_2_b.map.summary 	files in the output folder

quartus_fit --read_settings_files=off --write_settings_files=off lab_4_part_2_b -c lab_4_part_2_b
	#Fitter(Place & Route) which creates:
	#	lab_4_part_2_b.fit.rpt, 
	#	lab_4_part_2_b.fit.smsg, 
	#	lab_4_part_2_b.fit.summary, 
	#	lab_4_part_2_b.pin 	files in the output folder

quartus_asm --read_settings_files=off --write_settings_files=off lab_4_part_2_b -c lab_4_part_2_b
	#Assembler(Generate Programming Files) which creates:
	#	.jdi,
	#	.sof	files in the output folder

quartus_sta lab_4_part_2_b -c lab_4_part_2_b
	:TimeQuest Timing Analysis

jtagconfig –n
	:shows the list of jtag devices
	
nios2-configure-sof --cable --device 2 <output_files/filename.sof>
nios2-configure-sof -d 2 output_files/lab_4_part_2_b.sof
	:programs the FPGA chip using a .sof file

make -C software/nios_1 all
	
nios2-download --cable --device --go <filename.elf>
nios2-download -g nios_1.elf
	:program a nios2 processor using a .elf file

nios2-stackreport 
	:returns a report on the amount of memory still available for stack or heap based on .elf file
	:it does not take into account the stack or heap space the code consumes when it's running!
	
Notes: 
	.sof file is used to program the fpga and is located in the output_files directory inside the project working directory.
	.elf file is used to progr
	am the NIOS processor and is located in the
	
jtagconfig 												// to see the jtag devices available
nios2-configure-sof -d 2 intro_to_qsys_tutorial.sof		// to program the FPGA
nios2-download -g nios_system_1.elf						// to program the NIOS processor

cd Users/e313837/Desktop/WORKING_DIRECTORY_YET_TO_BACKUP/Task_15_Architecture_CTI_Reports_to_SACP


make -C soft/nios_bsp clean && make -C soft/nios_bsp all && make -C soft/nios clean && make -C soft/nios all
nios2-configure-sof -d 2 syn/output_files/Avalon_MM_to_Avalon_ST.sof
nios2-download -g soft/nios/nios.elf


make -C source/ip/CTI_Report/sim/soft/nios clean 1>>log.txt 2>>log.txt && make -C source/ip/CTI_Report/sim/soft/nios all 1>>log.txt 2>>log.txt


c:/altera/14.1/quartus/bin64/quartus DE1_SoC_SDRAM_Nios_Test.qpf &
c:/altera/14.1/quartus/sopc_builder/bin/qsys-edit DE1_SoC_QSYS.qsys &
c:/altera/14.1/quartus/sopc_builder/bin/qsys-edit /cygdrive/z/Z DRIVE/LEARNING/Altera Unviersity/Cyclone_V/CD/Demonstrations/FPGA/DE1_SoC_SDRAM_Nios_Test/DE1_SoC_QSYS.qsys &

make -C soft/nios_bsp clean && make -C soft/nios_bsp all && make -C soft/nios clean && make -C soft/nios all
nios2-configure-sof -d 2 syn/output_files/Avalon_MM_to_Avalon_ST.sof
nios2-download -g soft/nios/nios.elf

quartus column/tac/hw/fpga/syn/column_top.qpf &
qsys-edit column/tac/hw/fpga/source/qsys/ethernet_nic.qsys &
ls -la /opt/users/aaleyan/cti_report_column_0/column/tac/hw/fpga/source/ip/etherSL2_r1t1_subsystem/qsys/ethersl2_r1t1_ss/synthesis/
cp -rv ethersl2_r1t1_ss/ ethersl2_r1t1_ss.sopcinfo /vob/issr/column/tac/hw/fpga/source/ip/etherSL2_r1t1_subsystem/qsys/
ct lsco -r -me | sort
ct unco path_to_file/file

column\tac\build\fpga_sw\latest\@metadata
issr_idd\msgs  

/cygdrive/m/aaleyan_COLUMN_issr_build3.2/issr/column/tac/hw/fpga/source/ip/cti_report
M:\aaleyan_COLUMN_issr_build3.2\issr\column\tac\hw\fpga\source\ip\cti_report\soft

Expanding from 8 Dynamic words to 10 Dynamic words.



hw_cti_report_radartime

Generate the BSP to update the Makefile, and then build again.

To generate from the command line:
 nios2-bsp-generate-files --settings=<settings file> --bsp-dir=<target bsp files directory>

To establish serial connection to the NIOS via JTAG:
jtag-config
nios2-terminal DEVICE_NUMBER