Configure Hardware using Qsys

If, for whatever reason that you need to make changes to the hardware configuration of the FPGA, modification of the SOPC file is done through a program called Qsys.

How to edit SOPC file

1. Locate the *.qpf file in /[project folder]/FPGA/ and open the file
2. Once Quartus is launched, click on the Qsys button (circled red below)
3. Browse for the SOPC file that you would like to edit
4. Make changes to the hardware configuration as needed. Ensure no errors appear under the Messages pane.
5. When modifications are completed, go to Generate > Generate...
6. In the Generation window, ensure Simulation and Testbench System dropdown menu have None selected and Synthesis has Verilog selected.
7. Click Generate
8. Wait for awhile until the dialog says completed (below)
9. Click Close and go to File > Save
10. You may now close Qsys and go back to Quartus.
11. To regenerate the hardware files, click the Start Compilation button (circled red below)
12. Wait for about 10 minutes. The compilation is complete when the following message could be similarly seen in the logs: Info (293000): Quartus II Full Compilation was successful. 0 errors, 496 warnings
13. Done. Proceed to rebuilding the BSP