Xilinx GEM - acontis/atemsys GitHub Wiki
This page covers the link layer GEM from Xilinx. The link layer is built into the Zynq-7000 and Zynq Ultrascale+ SoC families, among others.
The acontis internal name for this link layer is emllGEM
ethernet@e000b000 {
compatible = "atemsys", "cdns,zynq-gem", "cdns,gem";
atemsys-Ident = "GEM";
atemsys-Instance = <0x1>;
reg = <0xe000b000 0x1000>;
status = "okay";
interrupts = <0x0 0x16 0x4>;
clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
phy-handle = <0xb>;
pinctrl-names = "default";
pinctrl-0 = <0xc>;
phy-reset-gpio = <0x9 0xb 0x0>;
phy-reset-active-low;
enet-reset = <0x9 0xb 0x0>;
phy-mode = "rgmii-id";
xlnx,ptp-enet-clock = <0x69f6bcb>;
local-mac-address = [00 0a 35 00 1e 53];
ethernet-phy@7 {
reg = <0x7>;
device_type = "ethernet-phy";
phandle = <0xb>;
};
};
ethernet@ff0e0000 {
compatible = "atemsys", "cdns,zynqmp-gem", "cdns,gem";
status = "okay";
atemsys-Ident = "GEM";
atemsys-Instance = <0x4>;
interrupt-parent = <0x4>;
interrupts = <0x0 0x3f 0x4 0x0 0x3f 0x4>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <0x1>;
#size-cells = <0x0>;
#stream-id-cells = <0x1>;
iommus = <0xe 0x877>;
power-domains = <0xc 0x20>;
clocks = <0x3 0x1f 0x3 0x6b 0x3 0x30 0x3 0x34 0x3 0x2c>;
phy-handle = <0xf>;
pinctrl-names = "default";
pinctrl-0 = <0x10>;
phy-mode = "rgmii-id";
xlnx,ptp-enet-clock = <0x0>;
local-mac-address = [00 0a 35 00 22 01];
phandle = <0x61>;
ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
phandle = <0xf>;
};
};