Synopsys DesignWare 3504 - acontis/atemsys GitHub Wiki

This page covers the link layer DW3505 from Synopsys. The link layer is built into several SoC's as IP core.

The acontis internal name for this link layer is emllDW3504

STM32MP157A-EV1


ethernet@5800a000 {
    compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a", "atemsys";
    atemsys-Ident = "DW3504";
    atemsys-Instance = <0x1>;
    reg = <0x5800a000 0x2000>;
    reg-names = "stmmaceth";
    interrupts-extended = <0x7 0x0 0x3d 0x4 0x12 0x46 0x4>;
    interrupt-names = "macirq", "eth_wake_irq";
    clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", "eth-ck", "ethstp";
    clocks = <0xc 0x69 0xc 0x67 0xc 0x68 0xc 0x7b 0xc 0x70>;
    st,syscon = <0xb 0x4>;
    snps,mixed-burst;
    snps,pbl = <0x2>;
    snps,en-tx-lpi-clockgating;
    snps,axi-config = <0x7e>;
    snps,tso;
    power-domains = <0x13>;
    status = "okay";
    pinctrl-0 = <0x7f>;
    pinctrl-1 = <0x80>;
    pinctrl-names = "default", "sleep";
    phy-mode = "rgmii-id";
    max-speed = <0x3e8>;
    phy-handle = <0x81>;
    nvmem-cells = <0x82>;
    nvmem-cell-names = "mac-address";
    phandle = <0x10f>;

    mdio0 {
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        compatible = "snps,dwmac-mdio";

        ethernet-phy@0 {
             reg = <0x0>;
             phandle = <0x81>;
        };
    };
};
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